Power semiconductor devices constitute the heart of modern power electronic apparatus. They are used in power electronic converters in the form of a matrix of on-off switches, and help to convert power from ac-to-dc (rectifier), dc-to-dc (chopper), dc-to-ac (inverter), and ac-to-ac at the same (ac controller) or different frequencies (cycloconverter). The switching mode power conversion gives high efficiency, but the disadvantage is that due to the nonlinearity of switches, harmonics are generated at both the supply and load sides. The switches are not ideal, and they have conduction and turn-on and turn-off switching losses. Converters are widely used in applications such as heating and lighting controls, ac and dc power supplies, electrochemical processes, dc and ac motor drives, static VAR generation, active harmonic filtering, etc. Although the cost of power semiconductor devices in power electronic equipment may hardly exceed 20–30 percent, the total equipment cost and performance may be highly influenced by the characteristics of the devices. An engineer designing equipment must understand the devices and their characteristics thoroughly in order to design efficient, reliable, and cost-effective systems with optimum performance. It is interesting to note that the modern technology evolution in power electronics has generally followed the evolution of power semiconductor devices. The advancement of microelectronics has greatly contributed to the knowledge of power device materials, processing, fabrication, packaging, modeling, and simulation. Today’s power semiconductor devices are almost exclusively based on silicon material and can be classified as follows:

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Power Semiconductor Devices

Conductivity Modulation in Semiconductor Structures Under Breakdown and Injection.- Standard and ESD Devices in Integrated Process Technologies.- ESD Clamps.- ESD Network Design Principles.- ESD Design for Signal Path Analog.- Power Management Circuits' ESD Protection.- System-Level and Discrete Components ESD.

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ESD Design for Analog Circuits

Overshoot voltages during VFTLP testing of DTSCRs are investigated. The DTSCRs in a 65nm process turn on at approximately 500ps. The overshoot voltages from DTSCRs are shown to cause gate oxide failures when gate oxide monitors were added in parallel to DTSCR ESD devices. Scaling trends show DTSCRs turning on at approximately 150ps when technologies are scaled down to the 32nm node.

Investigation of voltage overshoots in diode triggered silicon controlled rectifiers (DTSCRs) under very fast transmission line pulsing (VFTLP)

SCRs have been playing an increasingly significant role in ESD protection for CMOS technologies. A major challenge is to develop effective compact simulation models for these devices valid under ESD stress conditions. A simple macro modeling approach is presented for SPICE simulation of LVTSCR devices. The method uses advanced standard BJT and MOS models such as BSIM4 and Mextram. The simulation results have been verified using VFTLP and standard TLP measurements. The method provides a practical simulation tool for ESD protection circuits using LVTSCRs.

Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models

An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current. By controlling the gate current of the devices in the ESD detection circuit under a specified bias condition, the whole power-rail ESD clamp circuit can achieve an ultra-low standby leakage current. The new proposed circuit has been fabricated in a 1 V 65 nm CMOS process for experimental verification. The new proposed power-rail ESD clamp circuit can achieve 7 kV HBM and 325 V MM ESD levels while consuming only a standby leakage current of 96 nA at 1 V bias in room temperature and occupying an active area of only 49 mum 21 mum.

https://ir.nctu.edu.tw:443/bitstream/11536/7533/1/000263918900025.pdf

Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology

The authors compare a number of promising SCR-based ESD protection devices in 90nm and 65nm CMOS technologies implemented with a consistent layout. The devices are evaluated using ESD metrics such as trigger voltage and current, on-resistance, failure current, turn-on time and DC leakage current. The authors also report that SCR turn-on time is highly dependent on the amplitude of the applied pulse.

Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies

A scalable, compact model for SCR-based ESD-protection devices, which can simulate transient voltage overshoots observed on the timescale of charged device model (CDM) events, is presented. This model captures the effect that layout spacings have on SCR characteristics such as holding voltage and trigger current. Bias and time dependencies of SCR on-resistance are captured with a resistance model that accounts for self-heating and velocity saturation.

A scalable SCR compact model for ESD circuit simulation

A scalable compact model for SCR-based electrostatic discharge (ESD) protection devices is presented. This model captures the effect that layout spacing has on SCR characteristics, such as holding voltage and trigger current. The model also captures both the delayed turn-on of the SCR, which results in large voltage overshoots during fast rise-time ESD events and the charge removal mechanisms that underlie the turn-off transient. Bias and time dependences of SCR on-resistance are captured with a resistance model that accounts for self-heating.

A Scalable SCR Compact Model for ESD Circuit Simulation

A new dual-base triggered SCR is presented. By adjusting the device sizings in the trigger circuit, the designer sets the trigger voltage to an application appropriate-value. The turn on time is comparable to that of DTSCRs fabricated in the same technology node, but the leakage is orders of magnitude lower.

A dual-base triggered SCR with very low leakage current and adjustable trigger voltage

An oscillatory transmission line pulse generation system is introduced. This measurement system allows one to observe the response of an electrostatic discharge (ESD) protection device to a large-amplitude radio-frequency damped sinusoid; such waveforms mimic ESD tests. The trigger voltage of silicon-controlled rectifiers used for ESD protection is observed to be dependent on the past state of the device, due to charge storage in the bipolar bases.

J. Di Sarro

Papers

Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies

A scalable SCR compact model for ESD circuit simulation

A Scalable SCR Compact Model for ESD Circuit Simulation

A dual-base triggered SCR with very low leakage current and adjustable trigger voltage

Oscillatory Transmission Line Pulsing for Characterization of Device Transient Response