Current conveyors and related current-mode circuits have begun to emerge as an important class of circuits with properties that enable them to rival their voltage-mode counterparts in a wide range of applications. The use of current rather than voltage as the active parameter can result in higher usable gain, accuracy and bandwidth due to reduced voltage excursion at sensitive nodes. A current-mode approach is not just restricted to current processing, but also offers certain important advantages when interfaced to voltage-mode circuits. The author sets out to survey developments in conveyors and current-mode circuits from both an historical and technical viewpoint and to act as a useful source of reference material.

Recent developments in current conveyors and current-mode circuits

/pdf/design-for-reliability-of-low-voltage-switched-capacitor-1u86qo0h4a.pdf

Design for Reliability of Low-voltage, Switched-capacitor Circuits

Q-enhanced LC filter technology offers an alternative to the use of direct conversion techniques for implementing fully integrated receivers. Design and performance issues for QE LC filters are discussed and a fully integrated 850 MHz, two-pole, bandpass filter with an 18 MHz 3 dB bandwidth is reported. The prototype design is implemented in a standard 0.8 /spl mu/m CMOS process and achieves a rejection of over 50 dB at 100 MHz offset, an in-band dynamic range of 75 (90) dB when used in a system with a 1 MHz (30 kHz) final IF bandwidth, and a third-order intercept point that exceeds +25 dBm at an 80 MHz offset from the passband center,.

Q-enhanced LC bandpass filters for integrated wireless applications

A method and apparatus for analog-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional digital filtering techniques. In one embodiment, a sigma-delta ADC receives an analog input signal and converts the analog input signal to digital samples at an oversampling rate. A decimator, coupled to the sigma-delta ADC, receives the digital samples and decimates the digital samples to produce the digital samples at a preselected output sample rate, less than the oversampling rate. An ADC sample rate control circuit, coupled to the ADC, receives a frequency select signal representing the preselected output sample rate, and produces a noise-shaped clock signal for controlling operation of the ADC at the oversampling rate. The control circuit includes a sigma-delta modulator for sigma-delta modulating the frequency select signal. A randomizer/suppressor circuit, under control of the output of the sigma-delta modulator, receives an input clock signal and adjusts the frequency of the clock signal to produce a noise-shaped clock signal for controlling the oversampling rate of the ADC.

Variable sample rate adc

This paper proposes to study the design of a novel high-Q fully integrated switched capacitor bandpass filter. This circuit, implemented in CMOS technology, allows a tunable high selectivity over a broad frequency band. The proposed architecture is intended to replace passive surface acoustic wave (SAW) filters in low-cost wireless radio-communication applications. To show the feasibility of the proposed filter a prototype has been fabricated and tested. Measurements show quality factors up to 300, and a tunable center frequency range of 290 MHz [240 - 530 MHz] with a bandwidth tuning.

Fully Integrated High-Q Switched Capacitor Bandpass Filter with Center Frequency and Bandwidth Tuning

The design of GaAs MESFET technology is discussed. The design techniques developed are illustrated by means of a second-order switched-capacitor bandpass filter designed to operate at a switching frequency of 500 MHz. The design incorporates an operational amplifier architecture with a simulated gain of 60 dB and a switch driver circuit. Amplifiers are characterized in terms of settling time performance, and a general procedure for optimization of the switched-capacitor circuit to maximize switching frequency is presented. Measurements on a fabricated chip confirm the design of the filter and its components. >

Design optimization and testing of a GaAs switched-capacitor filter

The letter presents experimental results for a second order switched capacitor bandpass filter designed to operate with a 250 MHz switching frequency and implemented using gallium arsenide (GaAs) technology. Measurements on a chip fabricated in a 0.5 μm GaAs process confirm that the filter design, amplifier and switching components meet the desired performance specifications. The filter operates with high precision at 300 MHz and bandpass filtering at a switching frequency of 400 MHz is demonstrated.

400 MHz switching rate GaAs switched capacitor filter

The design procedures for integrated ladder filter design by operational simulation are regularized in terms of matrix operations. This analysis provides a systematic framework for the derivation of standard circuits such as leapfrog and coupled-biquad as well as several novel structures. Each circuit is seen to belong to a certain family, dependent on the type of matrix factorization used. A detailed comparison of the properties of the different structures is undertaken for a range of filter specifications, demonstrating that ladder filters offer good solutions to several difficult filtering problems. The methods are applicable to all active filter technologies including active-RC and switched capacitor. >

A methodology for integrated ladder filter design

A Methodology for Integrated Ladder Filter Design

A new design method for switched-capacitor filters (SCF) is presented. It is based upon an LU matrix decomposition technique and has the distinct advantage of producing SC filter realizations containing no delay free loops. These are formed traditionally by capacitors and opamps in leapfrog realizations. It is demonstrated that this feature should render reduced dependence of the filter response to nonideal effects such as finite amplifier GB and switch resistance. Results from realistic leapfrog and LUD SC filter realizations confirm this.

J.I. Sewell

Papers

Design optimization and testing of a GaAs switched-capacitor filter

400 MHz switching rate GaAs switched capacitor filter

A methodology for integrated ladder filter design

A Methodology for Integrated Ladder Filter Design

The LUD approach to switched-capacitor filter design