2.2. Interface Trapping Effects 211 3. High-k Dielectric Materials for OFETs 212 3.1. Inorganic Dielectrics 212 3.1.1. Aluminum Oxide 213 3.1.2. Tantalum Oxide 215 3.1.3. Titanium Dioxide 216 3.1.4. Hafnium Dioxide 217 3.1.5. Zirconium Dioxide 218 3.1.6. Cerium Dioxide 218 3.2. Organic Dielectrics 218 3.2.1. Polymer Dielectrics 218 3.2.2. Self-Assembled Monoand Multilayers 225 3.3. Hybrid Dielectrics 227 3.3.1. Polymeric-Nanoparticle Composites 227 3.3.2. Inorganic-Organic Bilayers 232 3.3.3. Hybrid Solid Polymer Electrolytes 235 4. Summary 235 5. Acknowledgments 236 6. References 236

High-k organic, inorganic, and hybrid dielectrics for low-voltage organic field-effect transistors.

This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic logic and memory devices are reviewed, with emphasis on novel devices that are structurally distinct front conventional bulk CMOS logic and memory devices. Possible applications of nanoscale CMOS are examined, with a view to better defining the likely capabilities of future microelectronic systems. This analysis covers both data processing applications and nondata processing applications such as RF and imaging. Finally, we speculate on the future of CMOS for the coming 15-20 years.

Nanoscale CMOS

In this paper a review of the more "fundamental" concerns regarding the scaling of the gate dielectric in the ultrathin regime is presented. Material issues are discussed pertaining to the integration of silicon oxynitride and oxide/nitride stacked layers and how such films might reduce or minimize boron penetration problems and address leakage current and reliability concerns. A methodology is presented to calculate device and chip lifetimes for MOS structures on the basis of data extracted from voltage- and temperature-accelerated measurements. Some integration issues regarding higher-k materials are also discussed because of their ability to solve the scaling problem. However, difficulties are involved in integrating them into a CMOS process flow.

Scaling the gate dielectric: materials, integration, and reliability

Performance limits of silicon MOSFETs are examined by a simple analytical theory augmented by self-consistent Schrodinger-Poisson simulations. The on-current, transconductance, and drain-to-source resistance in the ballistic limit (which corresponds to the channel length approaching zero) are examined. The ballistic transconductance in the limit that the oxide thickness approaches zero is also examined. The results show that as the channel length approaches zero (which corresponds to the ballistic limit), the on-current and transconductance approach finite limiting values and the channel resistance approaches a finite minimum value. The source velocity can be as high as about 1.5/spl times/10/sup 7/ cm/s. The limiting on-current and transconductance are considerably higher than those deduced experimentally by a previous study of MOSFETs with channel lengths greater than 0.2 /spl mu/m. At the same time, the transconductance to current ratio is substantially lower than that of a bipolar transistor.

On the performance limits for Si MOSFETs: a theoretical study

In metal–oxide–semiconductor structures with polycrystalline Si gates, electrons in the inverted channel of the substrate scatter with electrons in the gate via long-range Coulomb interactions. For thin oxides, these interactions can cause a significant transfer of momentum from the channel to the gate, thus reducing the effective mobility of the two-dimensional electron gas in the substrate. We present calculations of the dispersion of the interface plasmons in poly-Si/SiO2/Si structures, comparing the results obtained in the long-wavelength limit to those obtained using the random-phase approximation. Employing the former model, we compute the effect of plasmon scattering on the effective electron mobility in Si inversion layers. We find a significant reduction of the mobility for oxides thinner than about 3 nm.

Long-range Coulomb interactions in small Si devices. Part II. Effective electron mobility in thin-oxide structures

Reports measurements of the DC characteristics of sub-100 nm nMOSFETs that employ low leakage ultra-thin gate oxides only 1-2 nm thick to achieve high current drive capability and transconductance We demonstrate that I/sub Dsat//spl ap/18 mA//spl mu/m can be achieved with a 60 nm gate at 15 V using a 13-14 nm gate oxide with a gate leakage current less than 20 nA//spl mu/m/sup 2/ Furthermore, we find that I/sub Dsat/ deteriorates for gate oxides thicker or thinner than this

J. Jackson

Papers

Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs