This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

2.2. Interface Trapping Effects 211 3. High-k Dielectric Materials for OFETs 212 3.1. Inorganic Dielectrics 212 3.1.1. Aluminum Oxide 213 3.1.2. Tantalum Oxide 215 3.1.3. Titanium Dioxide 216 3.1.4. Hafnium Dioxide 217 3.1.5. Zirconium Dioxide 218 3.1.6. Cerium Dioxide 218 3.2. Organic Dielectrics 218 3.2.1. Polymer Dielectrics 218 3.2.2. Self-Assembled Monoand Multilayers 225 3.3. Hybrid Dielectrics 227 3.3.1. Polymeric-Nanoparticle Composites 227 3.3.2. Inorganic-Organic Bilayers 232 3.3.3. Hybrid Solid Polymer Electrolytes 235 4. Summary 235 5. Acknowledgments 236 6. References 236

High-k organic, inorganic, and hybrid dielectrics for low-voltage organic field-effect transistors.

Silicon-based heterostructures have come a long way from the discovery of strain as a new and essential parameter for band structure engineering to the present state of electron and hole mobilities, which surpass those achieved in the traditional material combination by more than an order of magnitude and are rapidly approaching the best III - V heteromaterials. It is the purpose of this article to report on the most recent developments, and the performance level achieved to date in this material system, in a concise and critical manner. The first part of this review is concerned with the structural and electronic properties of the lattice-mismatched Si/SiGe heterostructure. Emphases are put on the effects of strain both on the band structure and on the band offsets, as well as on means to actually control the strain in a stack of heteroepitaxial layers. The second part is dedicated to the transport properties of low-dimensional carrier systems in Si/SiGe and Ge/SiGe heterostructures. The prospects and limitations of the different layer concepts are discussed in terms of scattering mechanisms and experimental results. This part also reviews the most recent magneto-transport experiments on quantum wires and quantum point contacts, which became possible by the enhanced mean free paths in these materials. The third part covers the device aspects of these high-mobility materials, which is of special interest, because silicon-based heterostructures can significantly enhance the performance level of contemporary Si devices without sacrificing the essential compatibility with standard Si technologies. The recent achievements in this application-driven research field, but also the foreseeable problems and limitations, are discussed, and an assessment of the possible role of such heterodevices in future microelectronic circuits is given.

http://iopscience.iop.org/article/10.1088/0268-1242/12/12/001/pdf

High-mobility Si and Ge structures

The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

The mechanical response of materials with spatial gradients in composition and structure is of considerable interest in disciplines as diverse as tribology, geology, optoelectronics, biomechanics, fracture mechanics, and nanotechnology. The damage and failure resistance of surfaces to normal and sliding contact or impact can be changed substantially through such gradients. This review assesses the current understanding of the resistance of graded materials to contact deformation and damage, and outlines future research directions and possible applications for graded materials.

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Graded Materials for Resistance to Contact Deformation and Damage

To obtain a large lattice constant on Si, we have grown compositionally graded GexSi1−x on Si. These buffer layers have been characterized with electron‐beam‐induced current, transmission electron microscopy, scanning electron microscopy, x‐ray diffraction, and photoluminescence to determine the extent of relaxation, the threading dislocation density, the surface morphology, and the optical properties. We have observed that it is possible to obtain completely relaxed GexSi1−x layers with 0.1<x<1, threading dislocation densities of 105–5 × 106 cm−2, and with bulk GexSi1−x optical properties. Calculations show that gradually graded layers grown at relatively high temperatures can remain in equilibrium throughout growth, thereby avoiding strain buildup and the introduction of more threading dislocations through dislocation nucleation. It is also shown that the degree of surface crosshatch is related to inhomogeneous strain fields in the epilayer and to the thickness at which dislocations are introduced. Thes...

Relaxed GexSi1−x structures for III–V integration with Si and high mobility two‐dimensional electron gases in Si

Modulation‐doped Si/GexSi1−x/Ge/GexSi1−x structures were fabricated in which a thin Ge layer was employed as the conduction channel for the two‐dimensional hole gas. The strained heterostructure was fabricated on top of a low threading dislocation density, totally relaxed, GexSi1−x buffer layer with a linearly graded Ge concentration profile. The best mobility of the two‐dimensional hole gas is 55 000 cm2/V s at 4.2 K with a concentration‐dependent hole effective mass of ≤0.10m0. The effect of the Ge/GeSi interface roughness on the 2DHG mobility was studied.

Very high mobility two‐dimensional hole gas in Si/GexSi1−x/Ge structures grown by molecular beam epitaxy

We study breakdown in high-quality 2-7 nm gate dielectrics, and find that soft breakdown becomes more likely for thinner oxides and for oxides stressed at lower voltages. For 2 nm oxides, an increase in gate noise is the only precise indication of soft breakdown. For many applications, devices should remain functional with the level of gate noise we have observed, after soft breakdown.

Ultra-thin gate dielectrics: they break down, but do they fail?

A heterostructure includes a stained epitaxial layer of either silicon or germanium that is located overlying a silicon substrate, with a spatially graded Ge x Si 1-x epitaxial layer overlain by a ungraded Ge x .sbsb.0 Si 1-x .sbsb.0 intervening between the silicon substrate and the strained layer. Such a heterostructure can serve as a foundation for such devices as surface emitting LEDs, either n-channel or p-channel silicon-based MODFETs, and either n-channel or p-channel silicon-based MOSFETs.

Semiconductor heterostructure devices with strained semiconductor layers

This work presents a physically-based model for anode hole injection which explains both the voltage polarity asymmetry and sub-threshold behavior of Fowler-Nordheim (FN) stress generated oxide damage down to low V/sub G/. Also, we have developed an n-well bias technique for PFETs which clearly establishes that this FN stress-induced damage is due to anode hole injection.

P.J. Silverman

Papers

Relaxed GexSi1−x structures for III–V integration with Si and high mobility two‐dimensional electron gases in Si

Very high mobility two‐dimensional hole gas in Si/GexSi1−x/Ge structures grown by molecular beam epitaxy

Ultra-thin gate dielectrics: they break down, but do they fail?

Semiconductor heterostructure devices with strained semiconductor layers

Explanation of stress-induced damage in thin oxides