H.-H. Vuong

TL;DR: In this article, the Vertical Replacement Gate (VRG) MOSFET was proposed, which combines a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and a high quality gate oxide grown on a single-crystal Si channel.

TL;DR: In this article, the authors demonstrate that I/sub Dsat/ deteriorates for gate oxides thicker or thinner than this, and they also show that the performance of sub-100 nm nMOSFETs deteriorates with gate oxide thickness of 1-2 nm.

TL;DR: In this paper, a coupled defect/impurity diffusion model was proposed to predict RSCE in transistors with very shallow or flat channel profiles, where diffusion broadening cannot be the mechanism.

TL;DR: In this article, a complementary approach, using both electrical device data and accurate process modeling, as well as analytical dopant profiling with secondary ion mass spectroscopy, was proposed to investigate important features of the phenomenon, such as dose dependence, detrapping, and transient enhanced diffusion effects.

TL;DR: In this article, the authors present a model which simulates the trapping of arsenic and boron dopants at the silicon-silicon dioxide interface, and demonstrate that this model gives significantly more accurate doping profiles for a wide range of PMOS devices, as characterized by the device threshold voltage.