Microelectrode arrays and microprobes have been widely utilized to measure neuronal activity, both in vitro and in vivo. The key advantage is the capability to record and stimulate neurons at multiple sites simultaneously. However, unlike the single-cell or single-channel resolution of intracellular recording, microelectrodes detect signals from all possible sources around the sensor. Here, we review the current understanding of microelectrode signals and the techniques for analyzing them. We introduce the ongoing advancements in microelectrode technology, with focus on achieving higher resolution and quality of recordings by means of monolithic integration with on-chip circuitry. We show how recent advanced microelectrode array measurement methods facilitate the understanding of single neurons as well as network function.

/pdf/revealing-neuronal-function-through-microelectrode-array-58c7v2fxfm.pdf

Revealing neuronal function through microelectrode array recordings

This paper reports a 128-channel neural recording integrated circuit (IC) with on-the-fly spike feature extraction and wireless telemetry. The chip consists of eight 16-channel front-end recording blocks, spike detection and feature extraction digital signal processor (DSP), ultra wideband (UWB) transmitter, and on-chip bias generators. Each recording channel has amplifiers with programmable gain and bandwidth to accommodate different types of biological signals. An analog-to-digital converter (ADC) shared by 16 amplifiers through time-multiplexing results in a balanced trade-off between the power consumption and chip area. A nonlinear energy operator (NEO) based spike detector is implemented for identifying spikes, which are further processed by a digital frequency-shaping filter. The computationally efficient spike detection and feature extraction algorithms attribute to an auspicious DSP implementation on-chip. UWB telemetry is designed to wirelessly transfer raw data from 128 recording channels at a data rate of 90 Mbit/s. The chip is realized in 0.35 mum complementary metal-oxide-semiconductor (CMOS) process with an area of 8.8 times 7.2 mm2 and consumes 6 mW by employing a sequential turn-on architecture that selectively powers off idle analog circuit blocks. The chip has been tested for electrical specifications and verified in an ex vivo biological environment.

A 128-Channel 6 mW Wireless Neural Recording IC With Spike Feature Extraction and UWB Transmitter

The optogenetic approach to gain control over neuronal excitability both in vitro and in vivo has emerged as a fascinating scientific tool to explore neuronal networks, but it also opens possibilities for developing novel treatment strategies for neurologic conditions. We have explored whether such an optogenetic approach using the light-driven halorhodopsin chloride pump from Natronomonas pharaonis (NpHR), modified for mammalian CNS expression to hyperpolarize central neurons, may inhibit excessive hyperexcitability and epileptiform activity. We show that a lentiviral vector containing the NpHR gene under the calcium/calmodulin-dependent protein kinase IIα promoter transduces principal cells of the hippocampus and cortex and hyperpolarizes these cells, preventing generation of action potentials and epileptiform activity during optical stimulation. This study proves a principle, that selective hyperpolarization of principal cortical neurons by NpHR is sufficient to curtail paroxysmal activity in transduced neurons and can inhibit stimulation train-induced bursting in hippocampal organotypic slice cultures, which represents a model tissue of pharmacoresistant epilepsy. This study demonstrates that the optogenetic approach may prove useful for controlling epileptiform activity and opens a future perspective to develop it into a strategy to treat epilepsy.

/pdf/optogenetic-control-of-epileptiform-activity-1wgrus3acw.pdf

Optogenetic control of epileptiform activity

We present a fully differential 128-channel integrated neural interface. It consists of an array of 8 X 16 low-power low-noise signal-recording and generation circuits for electrical neural activity monitoring and stimulation, respectively. The recording channel has two stages of signal amplification and conditioning with and a fully differential 8-b column-parallel successive approximation (SAR) analog-to-digital converter (ADC). The total measured power consumption of each recording channel, including the SAR ADC, is 15.5 ?W. The measured input-referred noise is 6.08 ? Vrms over a 5-kHz bandwidth, resulting in a noise efficiency factor of 5.6. The stimulation channel performs monophasic or biphasic voltage-mode stimulation, with a maximum stimulation current of 5 mA and a quiescent power dissipation of 51.5 ?W. The design is implemented in 0.35-?m complementary metal-oxide semiconductor technology with the channel pitch of 200 ?m for a total die size of 3.4 mm × 2.5 mm and a total power consumption of 9.33 mW. The neural interface was validated in in vitro recording of a low-Mg2+/high-K+ epileptic seizure model in an intact hippocampus of a mouse.

/pdf/the-128-channel-fully-differential-digital-integrated-neural-2de1s1iso7.pdf

The 128-Channel Fully Differential Digital Integrated Neural Recording and Stimulation Interface

We present an area-efficient neural signal-acquisition system that uses a digitally intensive architecture to reduce system area and enable operation from a 0.5 V supply. The architecture replaces ac coupling capacitors and analog filters with a dual mixed-signal servo loop, which allows simultaneous digitization of the action and local field potentials. A noise-efficient DAC topology and an compact, boxcar sampling ADC are used to cancel input offset and prevent noise folding while enabling “per-pixel” digitization, alleviating system-level complexity. Implemented in a 65 nm CMOS process, the prototype occupies 0.013 mm2 while consuming 5 μW and achieving 4.9 μVrms of input-referred noise in a 10 kHz bandwidth.

A 0.013 ${\hbox {mm}}^{2}$ , 5 $\mu\hbox{W}$ , DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply

A 3D microsystem for multi-site penetrating extracellular neural recording from the brain is presented. A 16 times 16-channel neural recording interface integrated prototype fabricated in 0.35 mum CMOS occupies 3.5 mm times 4.5 mm area. Each recording channel dissipates 15 muW of power with input-referred noise of 7 muVrms over 5 kHz bandwidth. A switched-capacitor delta read-out data compression circuit trades recording accuracy for the output data rate. An array of 1.5 mm platinum-coated microelectrodes is bonded directly onto the die. Results of in vitro experimental recordings from intact mouse hippocampus validate the circuit design and the on-chip electrode bonding technology.

/pdf/256-channel-neural-recording-and-delta-compression-3tc6voyxxw.pdf

256-Channel Neural Recording and Delta Compression Microsystem With 3D Electrodes

The CMOS image sensor computes two-dimensional convolution of video frames with a programmable digital kernel of up to 8 times 8 pixels in parallel directly on the focal plane. Three operations, a temporal difference, a multiplication and an accumulation are performed for each pixel readout. A dual-memory pixel stores two video frames. Selective pixel output sampling controlled by binary kernel coefficients implements binary-analog multiplication. Cross-pixel column-parallel bit-level accumulation and frame differencing are implemented by switched-capacitor integrators. Binary-weighted summation and concurrent quantization is performed by a bank of column-parallel multiplying analog-to-digital converters (MADCs). A simple digital adder performs row-wise accumulation during ADC readout. A 128 times 128 active pixel array integrated with a bank of 128 MADCs was fabricated in a 0.35 mum standard CMOS technology. The 4.4 mm times 2.9 mm prototype is experimentally validated in discrete wavelet transform (DWT) video compression and frame differencing.

/pdf/focal-plane-algorithmically-multiplying-cmos-computational-3k4vaushmp.pdf

Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor

A 256-channel integrated interface for simultaneous recording of distributed neural activity from acute brain slices is presented. An array of 16 times 16 Au recording electrodes are fabricated directly on the die. Each channel implements differential voltage acquisition, amplification and band-pass filtering. In-channel analog memory stores an electronic image of neural activity. A 3 mm times 4.5 mm integrated prototype fabricated in a 0.35-mum CMOS technology is experimentally validated in single-channel extracellular in vitro recordings from the hippocampus of mice and in multichannel simultaneous recordings in a controlled environment

/pdf/brain-silicon-interface-for-high-resolution-in-vitro-neural-5e7wst9a6p.pdf

Brain–Silicon Interface for High-Resolution in vitro Neural Recording

A 16times16-channel 3.5times4.5mm2 neural recording interface is fabricated in 0.35mum CMOS and is integrated with on-chip 3D Au and Pt microelectrodes. Each channel dissipates 15muW with an input-referred noise of 7muV over 5kHz bandwidth. A switched-capacitor delta read-out data-compression circuit trades recording accuracy for the output data rate. In-vitro experimental results validate the circuit design and the on-chip 3D electrode bonding technology

256-Channel Neural Recording Microsystem with On-Chip 3D Electrodes

We present a neural recording and spectral analysis integrated microsystem It is the instrumentational and computational core of an envisioned miniature implantable brain implant for automated epileptic seizure therapy The microsystem combines two functional blocks: the neural recording interface and the spectral analysis processor The neural interface contains 256 signal acquisition channels recording neural field potentials from an array of 16 /spl times/ 16 electrodes simultaneously, in a distributed fashion The spectral analysis processor computes a wavelet-based time-frequency map (spectrogram) of the neural recording We demonstrate the functionality of the integrated microsystem in real-time epileptic seizure monitoring and spectral analysis, as necessary for subsequent automated seizure prediction and prevention

/pdf/real-time-seizure-monitoring-and-spectral-analysis-1rela2n529.pdf

J.N.Y. Aziz

Papers

256-Channel Neural Recording and Delta Compression Microsystem With 3D Electrodes

Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor

Brain–Silicon Interface for High-Resolution in vitro Neural Recording

256-Channel Neural Recording Microsystem with On-Chip 3D Electrodes

Real-time seizure monitoring and spectral analysis microsystem