A /spl Delta//spl Sigma/ topology with reduced sensitivity to opamp nonlinearities is described. The technique is effective even for very low oversampling ratios, and can be used for any modulation order. Techniques for reducing other nonideal effects are also proposed.

Wideband low-distortion delta-sigma ADC topology

Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (/spl Delta//spl Sigma/) structures used in telecommunication and audio applications usually cannot satisfy the requirements of high absolute accuracy and very small offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has most advantages of the /spl Delta//spl Sigma/ converter, yet is capable of offset-free and accurate conversion. In this paper, theoretical and practical aspects of higher order incremental converters are discussed. The operating principles, topologies, specialized digital filter design methods, and circuit level issues are all addressed. It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved. The theoretical results are verified by showing design examples and simulation results.

Theory and applications of incremental /spl Delta//spl Sigma/ converters

This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

This paper describes the design of a low power, energy-efficient CMOS smart temperature sensor intended for RFID temperature sensing. The BJT-based sensor employs an energy- efficient 2nd-order zoom ADC, which combines a coarse 5-bit SAR conversion with a fine 10-bit ΔΣ conversion. Moreover, a new integration scheme is proposed that halves the conversion time, while requiring no extra supply current. To meet the stringent cost constraints on RFID tags, a fast voltage calibration technique is used, which can be carried out in only 200 msec. After batch calibration and an individual room-temperature calibration, the sensor achieves an inaccuracy of ±0.15°C (3σ) from -55°C to 125°C . Over the same range, devices from a second lot achieved an inaccuracy of ±0.25°C (3σ) in both ceramic and plastic packages. The sensor occupies 0.08 mm2 in a 0.16 μm CMOS process, draws 3.4 μA from a 1.5 V to 2 V supply, and achieves a resolution of 20 mK in a conversion time of 5.3 msec. This corresponds to a minimum energy dissipation of 27 nJ per conversion.

/pdf/a-cmos-temperature-sensor-with-a-voltage-calibrated-55sw59cspt.pdf

A CMOS Temperature Sensor With a Voltage-Calibrated Inaccuracy of $\pm$ 0.15 $ ^{\circ}$ C (3 $\sigma$ ) From $-$ 55 $^{\circ}$ C to 125 $^{\circ}$ C

A CMOS image sensor architecture with built-in single-shot compressed sensing is described. The image sensor employs a conventional 4-T pixel and per-column ΣΔ ADCs. The compressed sensing measurements are obtained via a column multiplexer that sequentially applies randomly selected pixel values to the input of each ΣΔ modulator. At the end of readout, each ADC outputs a quantized value of the average of the pixel values applied to its input. The image is recovered from the random linear measurements off-chip using numerical optimization algorithms. To demonstrate this architecture, a 256x256 pixel CMOS image sensor is fabricated in 0.15 μm CIS process. The sensor can operate in compressed sensing mode with compression ratio 1/4, 1/8, or 1/16 at 480, 960, or 1920 fps, respectively, or in normal capture mode with no compressed sensing at a maximum frame rate of 120 fps. Measurement results demonstrate capture in compressed sensing mode at roughly the same readout noise of 351 μVrms and power consumption of 96.2 mW of normal capture at 120 fps. This performance is achieved with only 1.8% die area overhead. Image reconstruction shows modest quality loss relative to normal capture and significantly higher image quality than downsampling.

/pdf/cmos-image-sensor-with-per-column-sd-adc-and-programmable-4fjz1c6coh.pdf

CMOS Image Sensor With Per-Column ΣΔ ADC and Programmable Compressed Sensing

A background calibration method for enhancing the accuracy and linearity of a switched-capacitor digital-to-analogue converter is described. The method can be used alone or in combination with mismatch shaping to achieve very high accuracy and linearity combined with high speed.

Switched-capacitor DAC with analogue mismatch correction

Two digital techniques are described in this tutorial, both aimed at improving the accuracy of delta-sigma data converters. The first one corrects adaptively for mismatch errors in a MASH ADC, while the other acquires and then corrects for the nonlinearity of the internal multibit DAC used in the ADC.

/pdf/digital-techniques-for-improved-spl-delta-spl-sigma-data-1z1w6dsm2l.pdf

Digital techniques for improved /spl Delta//spl Sigma/ data conversion

A switched-R-MOSFET-C filter with tunable corner frequency is described. The tunability is achieved by varying the clock duty cycle using an automatic tuning circuit. This tuning method does not involve a change in any gate voltage, and is therefore particularly suitable for low-voltage and high-linearity applications. The advantages of the proposed method are illustrated with the design and simulation of a high-Q biquad filter.

/pdf/a-tunable-duty-cycle-controlled-switched-r-mosfet-c-cmos-5cqfj85jje.pdf

A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications

A/D converters used in instrumentation and measurements often require high absolute accuracy, including high linearity and negligible DC offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has all the advantages of the /spl Delta//spl Sigma/ (Delta-Sigma) converter, yet is capable of offset-free and accurate conversion. In this conference paper, theoretical and practical aspects of higher-order incremental converters are discussed. Operating principles, topologies and specialized digital filter design methods are addressed. The theoretical results are verified by showing design examples and simulation results.

/pdf/design-theory-for-high-order-incremental-converters-3f7v6yuidg.pdf

Design theory for high-order incremental converters

Cascaded delta-sigma (MASH) converters offer a good compromise between high accuracy, robust stability and speed. However, they are very sensitive to analog circuit imperfections. This paper presents an improved adaptive on-line digital compensation of these errors. Behavioral and circuit-level simulations have confirmed an achievable 13 bit performance and 6 MHz bandwidth for the proposed ADC.

/pdf/improved-adaptive-digital-compensation-for-cascaded-spl-1dr6ixko76.pdf

J. Silva

Papers

Switched-capacitor DAC with analogue mismatch correction

Digital techniques for improved /spl Delta//spl Sigma/ data conversion

A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications

Design theory for high-order incremental converters

Improved adaptive digital compensation for cascaded /spl Delta//spl Sigma/ ADCs