This tutorial presents an overview of the technological advances in millimeter-wave (mm-wave) circuit components, antennas, and propagation that will soon allow 60-GHz transceivers to provide multigigabit per second (multi-Gb/s) wireless communication data transfers in the consumer marketplace. Our goal is to help engineers understand the convergence of communications, circuits, and antennas, as the emerging world of subterahertz and terahertz wireless communications will require understanding at the intersections of these areas. This paper covers trends and recent accomplishments in a wide range of circuits and systems topics that must be understood to create massively broadband wireless communication systems of the future. In this paper, we present some evolving applications of massively broadband wireless communications, and use tables and graphs to show research progress from the literature on various radio system components, including on-chip and in-package antennas, radio-frequency (RF) power amplifiers (PAs), low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers, and analog-to-digital converters (ADCs). We focus primarily on silicon-based technologies, as these provide the best means of implementing very low-cost, highly integrated 60-GHz mm-wave circuits. In addition, the paper illuminates characterization techniques that are required to competently design and fabricate mm-wave devices in silicon, and illustrates effects of the 60-GHz RF propagation channel for both in-building and outdoor use. The paper concludes with an overview of the standardization and commercialization efforts for 60-GHz multi-Gb/s devices, and presents a novel way to compare the data rate versus power efficiency for future broadband devices.

http://faculty.poly.edu/~tsr/wp-content/uploads/publications/abstract17.pdf

State of the Art in 60-GHz Integrated Circuits and Systems for Wireless Communications

A large-scale monolithic silicon nanophotonic phased array on a chip creates and dynamically steers a high-resolution optical beam in free space, enabling emerging applications in sensing, imaging, and communication. The scalable architecture leverages sub-array structure, mitigating the impact of process variation on the phased array performance. In addition, sharing control electronics among multiple optical modulators in the scalable architecture reduces the number of digital-to-analog converters (DACs) required for an $N^{2}$ array from $\mathcal {O}(N^{2})$ to $\mathcal {O}(N)$ , allowing a small silicon footprint. An optical phased array for 1550-nm wavelength with 1024 uniformly spaced optical grating antennas, 1192 optical variable phase shifters, and 168 optical variable attenuators is integrated into a 5.7 mm $\times$ 6.4 mm chip in a commercial 180-nm silicon-on-insulator RF CMOS technology. The control signals for the optical variable phase shifters and attenuators are provided by 136 DACs with 14-bit nonuniform resolution using 2.5-V input-output transistors. The implemented phased array can create 0.03° narrow optical beams that can be steered unambiguously within ±22.5°.

A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS

A fully integrated switched-capacitor power amplifier (SCPA) utilizes switched-capacitor techniques in an EER/Polar architecture. It operates on the envelope of a nonconstant envelope modulated signal as an RF-DAC in order to amplify the signal efficiently. The measured maximum output power and PAE are 25.2 dBm and 45%, respectively. When amplifying an 802.11g 64-QAM orthogonal frequency-division multiplexing (OFDM) signal, the measured error vector magnitude is 2.6% and the average output power and power-added efficiencies are 17.7 dBm and 27%, respectively.

A Switched-Capacitor RF Power Amplifier

This paper surveys and discusses the state-of-the-art of integrated switched-capacitor and inductive power converters. After introducing applications that drive the need for integrated switching power converters, implementation issues to be addressed for integrated switched-capacitor and inductive converters are given, as well as design examples. At the end of this paper, a comprehensive set of integrated power converters are compared in terms of the main specifications and performance metrics, thereby allowing a categorization and providing application-oriented design guidelines.

Survey and Benchmark of Fully Integrated Switching Power Converters: Switched-Capacitor Versus Inductive Approach

We present a 2.4-GHz asymmetric multilevel outphasing (AMO) power amplifier (PA) with class-E branch amplifiers and discrete supply modulators integrated in a 65-nm CMOS process. AMO PAs achieve improved modulation bandwidth and efficiency over envelope tracking (ET) PAs by replacing the continuous supply modulator with a discrete supply modulator implemented with a fast digital switching network. Outphasing modulation is used to provide the required fine output envelope control. The AMO PA delivers 27.7-dBm peak output power with 45% system efficiency at 2.4 GHz. For a 20-MHz WLAN OFDM signal with 7.5-dB PAPR, the AMO PA achieves a drain efficiency of 31.9% and a system efficiency of 27.6% with an EVM of 2.7% rms.

A 2.4-GHz, 27-dBm Asymmetric Multilevel Outphasing Power Amplifier in 65-nm CMOS

A 30 dBm single-ended class-E RF power amplifier (PA) is fabricated in a baseline 65 nm CMOS technology The PA is constructed as a cascode stage formed by a standard thin-oxide device and a dedicated novel high voltage extended-drain thick-oxide device Both devices are implemented without using additional masks or processing steps The proposed PA uses an innovative self-biasing technique to ensure high power-added efficiency (PAE) at both high output power (Pout) and power back-off levels At 2 GHz, the PA achieves a PAE of 60% at a Pout of 30 dBm and a PAE of 40% at 16 dB back-off Stress tests indicate the reliability of both the novel high voltage device and the design

A 65 nm CMOS 30 dBm Class-E RF Power Amplifier With 60% PAE and 40% PAE at 16 dB Back-Off

A 30 dBm single-ended class-E RF power amplifier (PA) is fabricated in 65 nm CMOS technology. The PA is a cascode stage formed by a standard thin-oxide device and a high voltage extended-drain thick-oxide device. Both devices are implemented in a standard sub-micron CMOS technology without using extra masks or processing steps. The proposed PA uses an innovative self-biasing technique to ensure high power-added efficiency (PAE) at both high output power (Pout) and power back-off levels. At 2 GHz, the PA achieves a PAE of 60% at a Pout of 30 dBm and a PAE of 40% at 16 dB back-off.

A 65nm CMOS 30dBm class-E RF power amplifier with 60% power added efficiency

Trends in portable applications lead to integration of power management, power amplification and RF functionality in a single chip using the most advanced CMOS technology. The required HV transistors should be strictly realized in baseline CMOS to guarantee cost competitiveness and short time-to-market. This paper advocates innovative transistor architectures based on smart layout to address this challenge in both bulk and PD-SOI sub-100 nm CMOS.

Innovative High Voltage transistors for complex HV/RF SoCs in baseline CMOS

State-of-the-art wireless communication radios are implemented in deep-submi-cron CMOS, including the RF power amplifiers (PAs). However, in wireless infrastructure systems, the RF PA is often realized in an LDMOS or a compound technology to obtain the required large output powers. For next-generation reconfigurable infrastructure systems, the switch-mode PAs (SMPA) seem to offer the required flexibility for multiband multimode transmitters. In order to interface the high-power devices of the SMPA with the digital CMOS blocks of the transmitter, a wideband RF CMOS driver capable to generate high voltage (HV) swings is required. In this way, digital signal processing can be directly applied to control the required input pulse shapes of the SMPA.

A 65nm CMOS pulse-width-controlled driver with 8V pp output voltage for switch-mode RF PAs up to 3.6GHz

This paper demonstrates experimentally a novel design of medium voltage MOSFETs in 65 nm baseline low- voltage CMOS with state-of-the-art Ron performance. The HV capability is achieved through layout innovation independently from the available process. We demonstrate that gate fingers on STI regions interleaving the drain extension can be used as field plates enhancing the reverse voltage capability of EDMOS transistors. In this layout definition of lateral field plates, the effective field plate capacitance is determined by the lateral distance between the gate finger and the drain extension. Such an implementation allows process-less field plate capacitors graded along the drain extension enabling more flexible electrical field shaping as compared to classical field plates in the dielectric stack. A substantial (~1.65x) improvement of Ron vs. BVds is demonstrated with such gate finger field plates.

J. Sonsky

Papers

A 65 nm CMOS 30 dBm Class-E RF Power Amplifier With 60% PAE and 40% PAE at 16 dB Back-Off

A 65nm CMOS 30dBm class-E RF power amplifier with 60% power added efficiency

Innovative High Voltage transistors for complex HV/RF SoCs in baseline CMOS

A 65nm CMOS pulse-width-controlled driver with 8V pp output voltage for switch-mode RF PAs up to 3.6GHz

Innovative lateral field plates by gate fingers on STI regions in deep submicron CMOS