This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs A simplified theoretical analysis for the oscillation frequency and phase noise displayed by the QVCO in the 1/f/sup 3/ region is developed, and good agreement is found between theory and simulation results A prototype for the QVCO was implemented in a 035-/spl mu/m CMOS process with three standard metal layers The QVCO could be tuned between 164 and 197 GHz, and showed a phase noise of -140 dBc/Hz or less across the tuning range at a 3-MHz offset frequency from the carrier, for a current consumption of 25 mA from a 2-V power supply The equivalent phase error between I and Q signals was at most 025/spl deg/

/pdf/analysis-and-design-of-a-1-8-ghz-cmos-lc-quadrature-vco-3tacbqcgff.pdf

Analysis and design of a 1.8-GHz CMOS LC quadrature VCO

A new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5-GHz CMOS voltage-controlled oscillator (VCO). It uses the second harmonic of the outputs to couple the oscillators. The technique provides quadrature over a wide tuning range without introducing any increase in phase noise or power consumption. The VCO is tunable between 4.57 and 5.21 GHz and has a phase noise lower than -124 dBc/Hz at 1-MHz offset over the entire tuning range. The worst-case measured image rejection is 33 dB. The circuit draws 8.75 mA from a 2.5-V supply.

/pdf/a-low-phase-noise-5-ghz-cmos-quadrature-vco-using-582qevjd7j.pdf

A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling

We show that the quadrature LC oscillator is best treated as two strongly coupled, nominally identical oscillators that are locked to the same frequency. Differential equations that extend Adler's description of locking to strong injection reveal the full dynamics of this circuit. With a simplifying insight, the analysis reveals all the modes of the oscillator, their stability, the effects of mismatch on quadrature phase accuracy, and through a novel use of the analysis, phase noise.

The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking

Radio frequency integrated circuits (RFICs) are the building blocks that enable every device from cable television sets to mobile telephones to transmit and receive signals and data. This newly revised and expanded edition of the 2003 Artech House classic, "Radio Frequency Integrated Circuit Design", serves as an up-to-date, practical reference for complete RFIC know-how. The second edition includes numerous updates, including greater coverage of CMOS PA design, RFIC design with on-chip components, and more worked examples with simulation results. By emphasizing working designs, this book practically transports readers into the authors' own RFIC lab so they can fully understand how these designs function. This title is suitable for radio frequency integrated circuit (RFIC) design engineers; radio systems architects; researchers and developers of RFIC technology; and, graduate level electrical engineering students.

Radio Frequency Integrated Circuit Design

A single-chip 2.4-GHz CMOS radio transceiver with integrated baseband processing according to the IEEE 802.15.4 standard is presented. The transceiver consumes 14.7 mA in receive mode and 15.7 mA in transmit mode. The receiver uses a low-IF topology for high sensitivity and low power consumption, and achieves -101 dBm sensitivity for 1% packet error rate. The transmitter topology is based on a PLL direct-modulation scheme. Optimizations of architecture and circuit design level in order to reduce the transceiver power consumption are described. Special attention is paid to the RF front-end design which consumes 2.4mA in receive mode and features bidirectional RF pins. The 5.77 mm2 chip is implemented in a standard 0.18-mum CMOS technology. The transmitter delivers +3 dBm into the 100-Omega differential antenna port

A Fully Integrated 2.4-GHz IEEE 802.15.4-Compliant Transceiver for ZigBee™ Applications

Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-/spl mu/m CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 /spl mu/m/spl times/200 /spl mu/m. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW.

/pdf/a-low-voltage-folded-switching-mixer-in-0-18-spl-mu-m-cmos-2ta73zs940.pdf

A low-voltage folded-switching mixer in 0.18-/spl mu/m CMOS

A 5-GHz quadrature LC oscillator has been realized, in which the two LC stages are coupled with phase shifters. Analysis on the behavioral level shows that an N-stage LC oscillator is optimally coupled when each stage is connected with phase shifters providing /spl plusmn/180/spl deg//N phase shift. Simulation of the 5-GHz two-stage quadrature LC oscillator reveals a 4.3-dB reduction in phase noise compared to a quadrature LC oscillator without phase shifters. Measurements of the 5-GHz quadrature LC oscillator, made in a 30-GHz f/sub T/ process, show a phase noise lower than -113 dBc/Hz, with a resonator quality factor of only 4 and an oscillator core power dissipation of 21.2 mW.

Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator

The design of a multi-band low noise amplifier (LNA) is the first obstacle towards the design of a multi-standard receiver. In this paper, an approach for the design of a multi-band LNA for DECT and Bluetooth is presented. The formula for a minimal noise factor of a LNA, that takes into account the finite quality factor of the inductors is derived and the full design procedure that facilitates the design of a fully integrated LNA is given. The main advantages of the presented multi-band LNA are: high level of integration, reduced chip area by using only one integrated inductor, while the other is implemented as a bond-wire, input matching at two frequencies while having low noise figure, moderate voltage gain and good linearity. In DECT mode the simulated LNA performance is: NF = 2.2 dB, gain = 17 dB, IIP3 = 0.5 dBm, with a current of 8 mA, while in Bluetooth mode the LNA achieves: NF = 2.3 dB, gain = 15 dB, IIP3 = 3 dBm, with a current of only 4 mA.

Fully-integrated DECT/Bluetooth multi-band LNA in 0.18 /spl mu/m CMOS

A 5 GHz quadrature LC oscillator is realized which is based on a new architecture for multi-phase LC oscillators. Each section in the oscillator is coupled with an explicit phase shift of 180 degrees divided by the number of sections. Analysis on behavioral level shows that this maximizes the quality factor, and as a result, the carrier-to-noise ratio and robustness. An effective quality factor is derived which quantizes the degradation in phase noise performance if the sections of a multiphase LC oscillator are non-optimally coupled. The realized 5 GHz quadrature LC oscillator demonstrates that even at high frequencies the additional complexity of the proposed architecture yields a CNR improvement. The oscillator is realized in a BiCMOS process with a cut-off frequency of 30 GHz using an LC resonator with a quality factor of 4. A tuning range from 4.91 to 5.23 GHz is obtained with a CNR better than 113 dBc/Hz at 2 MHz offset. The VCO core power dissipation is only 21.2 mW at 2.7 V supply voltage.

https://www.vlsisymposium.org/Past/01web/circuits/cir_pdf/C11p2.pdf

An optimally coupled 5 GHz quadrature LC oscillator

This paper presents novel, explicit design equations for class-E power amplifiers with finite DC-feed inductance. A mathematically exact analysis of the idealized class-E power amplifier with small DC-feed inductance shows that the circuit element values are transcendent functions of the input parameters. Therefore, the designer needs to perform a long iterative procedure in order to find these values. We have solved the circuit operation for a certain number of cases, and performed a Lagrange polynomial interpolation in order to obtain explicit, directly usable design equations. The proposed design method is verified by simulation and the agreement with the theory is excellent.

J. van der Tang

Papers

A low-voltage folded-switching mixer in 0.18-/spl mu/m CMOS

Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator

Fully-integrated DECT/Bluetooth multi-band LNA in 0.18 /spl mu/m CMOS

An optimally coupled 5 GHz quadrature LC oscillator

Explicit design equations for class-E power amplifiers with small DC-feed inductance