Showing papers by "Jack T. Kavalieros published in 2015"

Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET

Abstract: Tunneling Field Effect Transistor (TFET) has attracted interest due to its steep-SS prospects [1]. Although a number of sub-60mV/dec TFETs were demonstrated [2], many failed to realize this feat due to non-optimized geometry, material choice [3], and material defects [4, 5]. In this paper, we clearly distinguish the requirement for i) geometry, ii) semiconductor BTBT characteristics, iii) semiconductor defects and iv) oxide interface defects. Using Ge as a case study, multi-temperature characterization of experimental PIN diodes is used to separate bulk properties from the interface effects, calibrating the models for BTBT, trap-assisted-tunneling (TAT) and SRH. The measured BTBT characteristic of a material is as important as the effect of defects; even a zero-defect TFET using the calibrated Ge material requires thin body and thin oxide. Bulk SRH and TAT is found to be a less critical issue for thin body TFETs, whereas interface defect density ∼1012cm−2 is low enough to only degrade TFET SS <10mV/dec. The method of current component segmentation using multi-temperature short-intrinsic PIN diodes is essential for evaluation of materials for TFETs.

III-N material structure for gate-recessed transistors

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

Transistor fin formation via cladding on sacrificial core

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.

High-mobility semiconductor source/drain spacer

Abstract: Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.

High electron mobility transistors with localized sub-fin isolation

Abstract: Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.

Fabrication of non-planar igzo devices for improved electrostatics

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

Indium-rich nmos transistor channels

Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.

High-electron-mobility transistors with heterojunction dopant diffusion barrier

Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A heterojunction between an active region of III-V semiconductor and the substrate provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where the silicon might otherwise behave as an electrically active amphoteric contaminate. In some embodiments, the heterojunction is provided within a base portion of a sub-fin disposed between the substrate and a fin containing a transistor channel region. The heterojunction positioned closer to the substrate than active fin region ensures thermal diffusion of silicon atoms is contained away from the active region of a III-V finFET.

High mobility field effect transistors with a retrograded semiconductor source/drain

Abstract: Monolithic FETs including a channel region of a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering the channel region, an impurity-doped compositionally graded semiconductor is grown, for example on at least a drain end of the channel region to introduce a carrier-blocking conduction band offset and/or a wider band gap within the drain region of the transistor. In some embodiments, the compositional grade induces a carrier-blocking band offset of at least 0.25 eV. The wider band gap and/or band offset contributes to a reduced gate induced drain leakage (GIDL). The impurity-doped semiconductor may be compositionally graded back down from the retrograded composition to a suitably narrow band gap material providing good ohmic contact. In some embodiments, the impurity-doped compositionally graded semiconductor growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.

Transistor with sub-fin dielectric region under a gate

Abstract: Embodiments of the present disclosure describe a semiconductor multi- gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The sub-fin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group lll-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group lll-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.

A transistor with a subfin layer

Abstract: A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing sidewalls. The fin comprises a first semiconductor material. The subfin layer comprises a III-V semiconductor material.

Transistor including tensile-strained germanium germanium channel

Abstract: Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p- type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n- MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).

Integration method for finfet with tightly controlled multiple fin heights

Abstract: A method including forming a fin of a nonplanar device on a substrate, the fin including a second layer between a first layer and a third layer; replacing the second layer with a dielectric material; and forming a gate stack on a channel region of the fin. An apparatus including a first multigate device on a substrate including a fin including a conducting layer on a dielectric layer, a gate stack disposed on the conducting layer in a channel region of the fin, and a source and a drain formed in the fin, and a second multigate device on the substrate including a fin including a first conducting layer and a second conducting layer separated by a dielectric layer, a gate stack disposed the first conducting layer and the second conducting layer in a channel region of the fin, and a source and a drain formed in the fin.

A method to achieve a uniform group iv material layer in an aspect ratio trapping trench

Abstract: Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material.

Apparatus and methods to create a buffer which extends into a gated region of a transistor

Abstract: Transistor devices may be formed having a buffer between an active channel and a substrate, wherein the active channel and a portion of the buffer form a gated region. The active channel may comprise a low band-gap material on a sub-structure, e.g. the buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electron mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure.

Methods for forming contacts to quantum well transistors

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a self-aligned contact of a quantum well structure, and an integrated circuit device.SOLUTION: A method for forming a self-aligned contact of a quantum well structure includes the steps of: depositing a metal layer on the quantum well structure; forming a gate trench by etching the metal layer and defining a source contact and a drain contact directly on each side surface of the gate trench from the metal layer; depositing s spacer layer on the side surface of the gate trench; and forming a gate electrode by depositing a gate electrode on the gate trench. The method further includes a step of depositing a high-k gate dielectric on a bottom of the gate trench. After the gate trench, the source contact, and the drain contact are formed, the spacer layer is deposited on the side surface of the gate trench, and the gate electrode is formed on the high-k gate dielectric.SELECTED DRAWING: Figure 8

Nanoscale structure with epitaxial film having a recessed bottom portion

Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.

Apparatus comprising semiconductor device, method for forming semiconductor device and computing system

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Apparatus having stacking transistors, method for fabricating stacking transistors and computing device

Abstract: Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.

Method for forming channel region of transistor, transistor and computing device

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

Transistor including tensile-strained germanium channel

Abstract: Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p- type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n- MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).

Tiefe Gate-Rundherum-Halbleitervorrichtung mit aktiver Germanium- oder Gruppe-III-V-Schicht

Abstract: Tiefe Gate-all-around-Halbleitervorrichtungen mit aktiven Germanium- oder Gruppe-III-V-Schichten werden beschrieben. Zum Beispiel umfasst eine nicht-planare Halbleitervorrichtung eine Hetero-Struktur uber einem Substrat. Die Hetero-Struktur weist einen Heteroubergang zwischen einer oberen Schicht und einer unteren Schicht unterschiedlicher Zusammensetzung auf. Eine aktive Schicht ist uber der Hetero-Struktur angeordnet und weist eine Zusammensetzung auf, die zu der der unteren und oberen Schicht der Hetero-Struktur unterschiedlich ist. Ein Gate-Elektroden-Stapel ist auf einem Kanal-Bereich der aktiven Schicht, diesen vollstandig umgebend, und in einem Graben in der oberen Schicht und zumindest teilweise in der unteren Schicht der Hetero-Struktur angeordnet. Source- und Drain-Bereiche sind in der aktiven Schicht und in der oberen Schicht, aber nicht in der unteren Schicht, auf beiden Seiten des Gate-Elektroden-Stapels angeordnet.

***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***Methods of containing defects for non-silicon device engineering

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Conductivity improvement in group iii-v semiconductor device

Abstract: PROBLEM TO BE SOLVED: To provide a method for reducing and minimizing the electrical resistance associated with the construction of a metal electrode upon a semiconductor material.SOLUTION: A method for forming a transistor includes steps of: forming a group III-V semiconductor stack by directly epitaxially forming a first III-V layer 213 on a III-V channel layer 210; etching the first III-V layer 213 at a position where a gate electrode 202 of a transistor is disposed and forming a void in the first III-V layer by the etching; epitaxially forming a barrier layer 209 in the void, the barrier layer filling the void; forming the gate electrode 202 above the barrier layer 209 and extending an end into the barrier layer 209, the end being closest to the III-V channel layer 210 of the gate electrode 202; and forming a source electrode 203 and a drain electrode 204 on the first III-V layer 213.

Multi-height finfet device by selective oxidation

Abstract: A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.