Electronics obtained through the bottom-up approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif. First, we will discuss representative electromechanical and resistance-change memory devices based on carbon nanotube and core-shell nanowire structures, respectively. These device structures show robust switching, promising performance metrics and the potential for terabit-scale density. Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally, bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional, vertically integrated multifunctional circuits, will be critically discussed.

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Nanoelectronics from the bottom up

Advances in top-down and bottom-up surface nanofabrication: techniques, applications & future prospects.

A lithographic apparatus configured to project a patterned beam of radiation onto a target portion of a substrate is disclosed. The apparatus includes a first radiation dose detector and a second radiation dose detector, each detector comprising a secondary electron emission surface configured to receive a radiation flux and to emit secondary electrons due to the receipt of the radiation flux, the first radiation dose detector located upstream with respect to the second radiation dose detector viewed with respect to a direction of radiation transmission, and a meter, connected to each detector, to detect a current or voltage resulting from the secondary electron emission from the respective electron emission surface.

Lithographic apparatus, and device manufacturing method

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

Double patterning lithography has been one of the candidates for sub-40nm patterning era, and has a lot of process
issues to be confirmed. Last year, we presented the issues in double patterning lithography with a real flash gate pattern.
Process flow was suggested and CD uniformity due to overlay was analyzed. And the layout decomposition and the two
types of double patterning of positive and negative tone were studied with 1-dimensional pattern. In this paper, the
implementation to DRAM patterns is examined, which consist of 2-dimensional patterns. Double patterning methods and
the selection of their tone for each layer are studied, and the difficulties from the randomness of core pattern are also
considered. As a result, DRAM patterns have more restrictions on the double patterning method and selection of tone,
and the aggressive layout decomposition should be designed to solve the difficulty in core patterning. Therefore, 37nm
DRAM layout can be patterned and the overlay control and cost still remain as dominant obstacles.

Issues and challenges of double patterning lithography in DRAM

Double patterning lithography is very fascinating way of lithography which is capable of pushing down the k1 limit below 0.25. By using double patterning lithography, we can delineate the pattern beyond resolution capability. Target pattern is decomposed into patterns within resolution capability and decomposed patterns are combined together through twice lithography and twice etch processes. Two ways, negative and positive, of doing double patterning process are contrived and studied experimentally. In this paper, various issues in double patterning lithography such as pattern decomposition, resist process on patterned topography, process window of 1/4 pitch patterning, and overlay dependent CD variation are studied on positive and negative tone double patterning respectively. Among various issues about double patterning, only the overlay controllability and productivity seemed to be dominated as visible obstacles so far.

Positive and negative tone double patterning lithography for 50nm flash memory

Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dry-etching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology

Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

The operating characteristics and retention times of floating body cells and arrays using Z-RAMreg technology fabricated on a 50 nm DRAM process are presented. For the first time, data retention time longer than 8 s at 93degC and 1.6 V wide programming window are obtained on floating body cells as small as 54 nm times 54 nm. These results demonstrate the suitability of floating body memories for DRAM applications. These improvements were obtained through optimization of DRAM technology such as junction engineering, thermal treatments, and improved passivation processes.

Highly scalable Z-RAM with remarkably long data retention for DRAM application

Recently, a new technology called double exposure lithography is emerging as new technology that extends lithography factor under 0.25. The need of this technology comes from the delay in maturity of EUV technology such as light source, reflective mask and optics, and resist. However, double exposure technology requires additional processes including two hard mask deposition steps, one more lithography patterning step and two hard mask etching steps. In addition, there would be several issues such as patterning on topology problems for the case of second patterning and complexity in etching process. In brief, the complex process of double exposure technology should be simplified for real device production. 
In this paper, we will introduce novel double exposure technology that minimizes the number of process steps by using silicon containing BARC. Silicon BARC acts as BARC and hard mask at the same time in our double exposure process so the process step and cost can be reduced. During first exposure step, silicon containing BARC take a role of BARC for first resist patterning and then remaining pattern of silicon containing BARC acts as hard mask pattern for second patterning and etching. Using this simple and novel process, more economic way of double exposure technology can be available. In this paper, the issues and countermeasures for silicon containing BARC based double exposure technology will be reported.

Seung-Chan Moon

Papers

Issues and challenges of double patterning lithography in DRAM

Positive and negative tone double patterning lithography for 50nm flash memory

Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

Highly scalable Z-RAM with remarkably long data retention for DRAM application

Double exposure technology using silicon containing materials