Proceedings ArticleDOI
Positive and negative tone double patterning lithography for 50nm flash memory
Chang-Moon Lim,Seo-Min Kim,Young-Sun Hwang,Jaeseung Choi,Keundo Ban,Sung-Yoon Cho,Jin-Ki Jung,Eung-Kil Kang,Hee-Youl Lim,Hyeong-Soo Kim,Seung-Chan Moon +10 more
- Vol. 6154, pp 363-370
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TLDR
In this article, various issues in double patterning lithography such as pattern decomposition, resist process on patterned topography, process window of 1/4 pitch patterning, and overlay dependent CD variation are studied on positive and negative tone double patterns respectively.Abstract:
Double patterning lithography is very fascinating way of lithography which is capable of pushing down the k1 limit below 0.25. By using double patterning lithography, we can delineate the pattern beyond resolution capability. Target pattern is decomposed into patterns within resolution capability and decomposed patterns are combined together through twice lithography and twice etch processes. Two ways, negative and positive, of doing double patterning process are contrived and studied experimentally. In this paper, various issues in double patterning lithography such as pattern decomposition, resist process on patterned topography, process window of 1/4 pitch patterning, and overlay dependent CD variation are studied on positive and negative tone double patterning respectively. Among various issues about double patterning, only the overlay controllability and productivity seemed to be dominated as visible obstacles so far.read more
Citations
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Proceedings ArticleDOI
Layout decomposition for triple patterning lithography
TL;DR: It is shown that TPL layout decomposition is a more difficult problem than that for DPL, and a novel vector programming formulation is proposed which can simultaneously minimize conflict and stitch numbers and solve it through effective semidefinite programming (SDP) approximation.
Proceedings ArticleDOI
Layout decomposition for double patterning lithography
Abstract: In double patterning lithography (DPL) layout decomposition for 45 nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing [11, 9, 5]. However, there exist pattern configurations for which pattern features separated by less than the minimum color spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using a layout decomposition algorithm that includes graph construction, conflict cycle detection, and node splitting processes. We evaluate our technique on both real-world and artificially generated test cases in 45 nm technology. Experimental results show that our proposed layout decomposition method effectively decomposes given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout.
Proceedings ArticleDOI
Issues and challenges of double patterning lithography in DRAM
Seo-Min Kim,Sunyoung Koo,Jaeseung Choi,Young-Sun Hwang,Jungwoo Park,Eung-Kil Kang,Chang-Moon Lim,Seung-Chan Moon,Jinwoong Kim +8 more
TL;DR: 37nm DRAM layout can be patterned and the overlay control and cost still remain as dominant obstacles, and the aggressive layout decomposition should be designed to solve the difficulty in core patterning.
Proceedings ArticleDOI
Manufacturability issues with double patterning for 50-nm half-pitch single damascene applications using RELACS shrink and corresponding OPC
Maaike Op de Beeck,Janko Versluijs,Vincent Wiaux,Tom Vandeweyer,Ivan Ciofi,Herbert Struyf,Dirk Hendrickx,Jan Van Olmen +7 more
TL;DR: In this paper, a double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-lithoetch approach on metal hard mask (MHM).
Proceedings ArticleDOI
Double Exposure Using 193nm Negative Tone Photoresist
TL;DR: In this article, double patterning of k 1-effective = 0.25 with improved process window using a negative resist was demonstrated, where two etch transfer steps were incorporated into the hard mask material and frequency doubled patterns could be obtained.
References
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Proceedings ArticleDOI
Study on the shoreline for water immersion ArF lithography
Chang-Moon Lim,Tae-Seung Eom,Seo-Min Kim,Cheol-Kyu Bok,Won-Kwang Ma,Gyu-Dong Park,Seung-Chan Moon,Jinwoong Kim +7 more
TL;DR: In this article, the authors compared the performance of immersion lithography in 80nm DRAM with that of conventional dry lithography through experiment and simulation, and the result of simulation is quite well matched with the experiment results.