Before the emergence of ultra-wideband (UWB) radios, widely used wireless communications were based on sinusoidal carriers, and impulse technologies were employed only in specific applications (e.g. radar). In 2002, the Federal Communication Commission (FCC) allowed unlicensed operation between 3.1–10.6 GHz for UWB communication, using a wideband signal format with a low EIRP level (−41.3dBm/MHz). UWB communication systems then emerged as an alternative to narrowband systems and significant effort in this area has been invested at the regulatory, commercial, and research levels.

IEEE Transactions on Microwave Theory and Techniques and Antennas and Propagation Announce a Joint Special Issue on Ultra-Wideband (UWB) Technology

We present high-performance integrated optical phased arrays along with first-of-their-kind light detection and ranging (LiDAR) and free-space data communication demonstrators. First, record-performance optical phased array components are shown with low-power phase shifters and high-directionality waveguide grating antennas. Then, one-dimensional (1-D) 512-element optical phased arrays are demonstrated with record low-power operation ( $ 1 mW total), large steering ranges, and high-speed two-dimensional (2-D) beam steering ( $ 30 $\mu$ s phase shifter time constant). Next, by utilizing optical phased arrays, we show coherent 2-D solid-state LiDAR on diffusive targets with simultaneous velocity extraction at a range of nearly 200 m. In addition, the first demonstration of 3-D coherent LiDAR with optical phased arrays is presented with raster-scanning arrays. Finally, lens-free chip-to-chip free-space optical communication links up to 50 m are shown, including a demonstration of a steerable transmitter to multiple optical phased array receivers at a 1 Gb/s data rate. This paper shows the most advanced silicon photonics solid-state beam steering to date with relevant demonstrators in practical applications.

Long-Range LiDAR and Free-Space Data Communication With High-Performance Optical Phased Arrays

A technology roadmap for the electrical performance of high-speed silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) is presented based on combining the results of various 1-D, 2-D, and 3-D technology computer-aided design (TCAD) simulation tools with geometry scalable compact modeling. The latter, including all known parasitic effects, enables the accurate determination of the figures of merit for both devices and selected benchmark circuits. The presented roadmap defines five major technology nodes with the maximum oscillation frequency of a typical high-frequency device structure as the main device design target under the constraints of various other parameters for generating the doping profiles and for defining the lateral scaling factors. An extensive and consistent set of technology and electrical parameters is provided along with the obtained scaling rules. The expected fabrication-related challenges and possible solutions for achieving the predicted performance are being discussed. It is hoped that the presented roadmap will be useful not only for foundries and equipment manufacturers but also for circuit and system designers enabling better predictions of the capability of SiGe–BiCMOS process technology for new millimeter-wave (mm-wave) and terahertz (THz) applications.

SiGe HBT Technology: Future Trends and TCAD-Based Roadmap

This paper presents a fully integrated 60 GHz direct-conversion transceiver in 45 nm SOI CMOS for same-channel full-duplex (FD) wireless communication. FD operation is enabled by a novel polarization-based wideband reconfigurable self-interference cancellation (SIC) technique in the antenna domain. The antenna cancellation can be reconfigured from the IC to combat the variable SI scattering from the environment during in-field operation. A second RF cancellation path with $ > 30\;\text{dB}$ gain control and $ > 360^{\circ}$ phase control from the transmitter (TX) output to the LNA output further suppresses the residual SI to achieve the high levels of required SIC. With antenna and RF cancellation together, a total SI suppression of $ > 70\;\text{dB}$ is achieved over a cancellation bandwidth of 1 GHz and can be maintained in the presence of nearby reflectors. In conjunction with digital SIC (DSIC) implemented in MATLAB, a FD link is demonstrated over 0.7 m with a signal-to-interference-noise-and-distortion ratio (SINDR) of 7.2 dB. To the best of our knowledge, this work achieves the highest integration level among FD transceivers irrespective of the operation frequency and demonstrates the first fully integrated mm-wave FD transceiver front-end and link.

A 60 GHz CMOS Full-Duplex Transceiver and Link with Polarization-Based Antenna and RF Cancellation

Series stacking of multiple devices is a promising technique that can help overcome some of the fundamental limitations of CMOS technology in order to improve the output power and efficiency of CMOS power amplifiers (PAs), particularly at millimeter-wave (mmWave) frequencies. This paper investigates the concept of device stacking in the context of the Class-E family of nonlinear switching PAs at mmWave frequencies. Fundamental limits on achievable performance of a stacked configuration are presented along with design guidelines for a practical implementation. In order to demonstrate the utility of stacking, three prototypes have been implemented: two fully integrated 45-GHz single-ended Class-E-like PAs with two- and four-stacked devices in IBM's 45-nm silicon-on-insulator (SOI) CMOS technology, and a 45-GHz differential Class-E-like PA with two devices stacked in IBM's 65-nm low-power CMOS process. Measurement results yield a peak power-added efficiency (PAE) of 34.6% for the two-stacked 45-nm SOI CMOS PA with a saturated output power of 17.6 dBm. The measurement results also indicate true Class-E-like switching PA behavior. A peak PAE of 19.4% is measured for the four-stacked PA with a saturated output power of 20.3 dBm. The two-stacked PA exhibits the highest PAE reported for CMOS mmWave PAs, and the four-stacked PA achieves the highest output power from a fully integrated CMOS mmWave PA including those that employ power combining. The 65-nm CMOS differential two-stacked PA exhibits a peak PAE of 28.3% with a saturated differential output power of 18.2 dBm, despite the poor ON-resistance of the 65-nm low-power nMOS devices. This paper also describes the modeling of active devices for mmWave CMOS PAs for good model-hardware correlation.

High-Power High-Efficiency Class-E-Like Stacked mmWave PAs in SOI and Bulk CMOS: Theory and Implementation

This paper introduces a Maximum Gain Ring Oscillator (MGRO) topology that maximizes the power gain achieved by the active devices using appropriately designed passive matching networks to maximize the frequency of oscillation. A design methodology is provided along with guidelines for the design of the passive matching network. In the absence of passive losses, the topology can oscillate at the f max of the active devices. In the presence of passive loss, the losses can be taken into account in a closed-form fashion to maximize oscillation frequency. Based on this topology, an oscillator operating at approximately 107.5GHz is implemented using the 56-nm body-contacted devices of IBM's 45nm SOI CMOS technology (f max is about 200GHz). The second harmonic of this oscillation is extracted using a load-pull-optimized, extraction network. This topology can be generalized for the extraction of any harmonic from MGROs with different number of stages. The oscillator generates −14.4dBm of power at 216.2GHz while drawing 57.5mW of DC power. The modeling of 45nm SOI devices for millimeter-wave design is also described.

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215GHz CMOS signal source based on a Maximum Gain Ring Oscillator topology

CMOS high-mmWave/sub-mmWave sources leverage device nonlinearity, either in oscillators or frequency multipliers, to generate harmonics beyond the technology f max . We propose a power mixer topology that exploits non-linearity engineering to enhance the output harmonic content. By engineering the amplitude and phase of the fundamental and second-harmonic content in the mixer device voltage waveforms, the output third harmonic power is enhanced significantly beyond that achievable in conventional frequency triplers. A 200 GHz power mixer in 130 nm CMOS generates 50 μW of output power at a frequency 1.5× higher than f max .

https://www.ee.columbia.edu/~harish/uploads/2/6/9/2/26925901/c22.pdf

A 200GHz power mixer in 130nm-CMOS employing nonlinearity engineering

As data rates continue to increase, the reach of electrical interconnects is becoming shorter due to loss and distortion of the signal. Optical interconnects based on vertical-cavity surface-emitting lasers (VCSELs) provide a cost-effective solution to transfer data over tens of meters in data centers. However, integrating optical transceivers within a server platform requires improved bandwidth density and energy efficiency. High data-rate, compact area, and energy-efficient transmitter (TX) circuits that mitigate VCSEL nonlinearity and bandwidth limitations are key enablers of this integration. This paper presents an optical TX implemented in 28nm bulk CMOS which drives an 850nm VCSEL up to 56Gb/s.

A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

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Current EO-PLLs for laser chirp modulation require large, lossy delay waveguides in an MZI to detect chirp slope. EO-PLLs, and electronic control loops generally, are dominantly digital. A new analog EO-PLL breaks the trade-off between chirp bandwidth and MZI delay, reducing area and loss by 10 x.

Jahnavi Sharma

Papers

215GHz CMOS signal source based on a Maximum Gain Ring Oscillator topology

A 200GHz power mixer in 130nm-CMOS employing nonlinearity engineering

A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

Continuous-Time Electro-Optic PLL with Decimated Optical Delay/Loss and Spur Cancellation for LIDAR