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Design Of Analog Cmos Integrated Circuits

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Design of Nanostructured Solar Cells Using Coupled Optical and Electrical Modeling Michael G. Deceglie † , Vivian E. Ferry ‡ , A. Paul Alivisatos ‡ , and Harry A. Atwater* ,† Thomas J. Watson Laboratories of Applied Physics, California Institute of Technology, Pasadena, California 91125, United States Materials Science Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720, United States Abstract: Nanostructured light trapping has emerged as a promising route toward improved efficiency in solar cells. We use coupled optical and electrical modeling to guide optimization of such nanostructures. We study thin-film n-i-p a-Si:H devices and demonstrate that nanostructures can be tailored to minimize absorption in the doped a-Si:H, improving carrier collection efficiency. This suggests a method for device optimization in which optical design not only maximizes absorption, but also ensures resulting carriers are efficiently collected. Keywords: Thin film solar cells, plasmon, nanophotonic, light trapping, simulation, device physics, silicon, photovoltaics In order to maximize solar cell efficiency, it is necessary to optimize both the electrical device physics and the optical absorption of the device. Typically, these two problems are treated separately,

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Design of Nanostructured Solar Cells Using Coupled Optical and Electrical Modeling - eScholarship

In this paper, we have investigated device reliability by studying the impact of interface traps, both donor (positive interface charges) and acceptor (negative interface charges), present at the Si/SiO2 interface, on analog/RF performance and linearity distortion analysis of heterogeneous-gate-dielectric gate-all-around tunnel FET (HD-GAA-TFET), which is used to enhance the tunneling current of TFET. Various figures of merit such as cutoff frequency $f_{{T}}$ , maximum oscillation frequency $f_{\max}$ , transconductance frequency product, higher order transconductance coefficients $({g}_{{m}1}, {g}_{{m}3})$ , VIP2, VIP3, IIP3, IMD3, zero crossover point, and 1-dB compression point have been investigated, and the results obtained are simultaneously compared with a gate-all-around TFET (GAA-TFET). Simulation results indicate that HD-GAA-TFET is more immune toward the interface trap charges present at the Si/SiO2 interface than the GAA TFET and hence can act as a better candidate for low power switching applications. All simulations have been done on an ATLAS device simulator.

Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability

Device simulation of 17.3% efficient lead-free all-perovskite tandem solar cell

This paper investigates the reliability of PIN-gate-all-around (GAA)-tunnel field-effect transistor (TFET) with N+ source pocket. The reliability of the PNIN-GAA-TFET is examined by analyzing: 1) the impact of interface trap charge (ITC) density and polarity and 2) the temperature affectability on analog/RF performance of the device. It is realized that the interface traps existing at the Si/SiO2 interface modifies the flatband voltage and, thereby, alters the analog and RF characteristics of the device. The analysis is done at various trap charge densities and polarities. The results, thus, obtained reveal that, at higher trap charge density, the device performance alters significantly. It is obtained that, for a donor trap charge density of $3 \times 10^{{12}}$ cm $^{-2}$ , the off-state current of the device degrades tremendously (increases from an order of $10^{-17}$ – $10^{-9}\text{A}$ ). The temperature affectability over the device reveals that, at lower gate bias, the Shockley–Read–Hall phenomenon dominates and degrades the subthreshold current of the device at elevated temperatures. However, for the superthreshold regime, the band-to-band tunneling (BTBT) mechanism dominates. Furthermore, the results show enormous degradation in the off-state current at elevated temperatures, such that, with an increase in the ambient temperature from 200 K to 400 K, the $I_{ \mathrm{\scriptscriptstyle OFF}}$ degrades by an order of $10^{5}$ , i.e., increases from $10^{-18}$ A to $10^{-13}$ A. The results specify that the PNIN-GAA-TFET is insusceptible to the acceptor traps existing at the Si/SiO2 interface in comparison with the donor traps.

Numerical Simulation of N + Source Pocket PIN-GAA-Tunnel FET: Impact of Interface Trap Charges and Temperature

Gate Drain Underlapped-PNIN-GAA-TFET for Comprehensively Upgraded Analog/RF Performance

The goal of this work is to overcome the major impediments of tunnel FET such as the inherent ambipolar current (I
 AMB) and the lower ON current (I
 ON). To suppress the I
 AMB, gate drain overlap (GDO) engineering scheme has been incorporated over the cylindrical gate all around TFET (GAA-TFET). However, to enhance the I
 ON, heterogate dielectrics (HD) are used in the gate oxide region. Results indicate that an appreciably reduced I
 AMB and significantly enhanced I
 ON has been obtained with the amalgamation of GDO and HD, respectively, onto GAA-TFET. Further, the effect of GDO length (L
 ov) has also been studied. Quantitative analysis of ambipolarity factor “α” reveals that at large L
 ov, “α” improves. It is found that GDO degrades the high-frequency (HF) performance such as cutoff frequency (f
 T) of the device, because of the enhanced parasitic capacitances. To surpass the deterioration at HF caused by GDO, the dielectric over GDO region has been altered, and it has been analyzed that by inserting a material of low-dielectric constant (k = 1) and parasitic capacitances of the device reduces, resulting into enhancement in f
 T. Moreover, the low-k dielectric inserted over L
 ov reduces the I
 AMB supplementary, along with enhanced f
 T. Suppressed I
 AMB and enhanced f
 T of GDO–HD–GAA-TFET with low-k dielectric over L
 ov make it adequate for application in HF and digital circuitry.

Jaya Madan

Papers

Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability

Device simulation of 17.3% efficient lead-free all-perovskite tandem solar cell

Numerical Simulation of N + Source Pocket PIN-GAA-Tunnel FET: Impact of Interface Trap Charges and Temperature

Gate Drain Underlapped-PNIN-GAA-TFET for Comprehensively Upgraded Analog/RF Performance

Gate drain-overlapped-asymmetric gate dielectric-GAA-TFET: a solution for suppressed ambipolarity and enhanced ON state behavior