The objective of this paper is to give a comprehensive introduction to applied cryptography with an engineer or computer scientist in mind. The emphasis is on the knowledge needed to create practical systems which supports integrity, confidentiality, or authenticity. Topics covered includes an introduction to the concepts in cryptography, attacks against cryptographic systems, key use and handling, random bit generation, encryption modes, and message authentication codes. Recommendations on algorithms and further reading is given in the end of the paper. This paper should make the reader able to build, understand and evaluate system descriptions and designs based on the cryptographic components described in the paper.

[서평]「Applied Cryptography」

We review a model of computation used in industrial practice in signal processing software environments and experimentally and other contexts. We give this model the name "dataflow process networks," and study its formal properties as well as its utility as a basis for programming language design. Variants of this model are used in commercial visual programming systems such as SPW from the Alta Group of Cadence (formerly Comdisco Systems), COSSAP from Synopsys (formerly Cadis), the DSP Station from Mentor Graphics, and Hypersignal from Hyperception. They are also used in research software such as Khoros from the University of New Mexico and Ptolemy from the University of California at Berkeley, among many others. Dataflow process networks are shown to be a special case of Kahn process networks, a model of computation where a number of concurrent processes communicate through unidirectional FIFO channels, where writes to the channel are nonblocking, and reads are blocking. In dataflow process networks, each process consists of repeated "firings" of a dataflow "actor." An actor defines a (often functional) quantum of computation. By dividing processes into actor firings, the considerable overhead of context switching incurred in most implementations of Kahn process networks is avoided. We relate dataflow process networks to other dataflow models, including those used in dataflow machines, such as static dataflow and the tagged-token model. We also relate dataflow process networks to functional languages such as Haskell, and show that modern language concepts such as higher-order functions and polymorphism can be used effectively in dataflow process networks. A number of programming examples using a visual syntax are given. >

/pdf/dataflow-process-networks-3mdwy0uhx2.pdf

Dataflow process networks

The rapid uptake of mobile devices and the rising popularity of mobile applications and services pose unprecedented demands on mobile and wireless networking infrastructure. Upcoming 5G systems are evolving to support exploding mobile traffic volumes, real-time extraction of fine-grained analytics, and agile management of network resources, so as to maximize user experience. Fulfilling these tasks is challenging, as mobile environments are increasingly complex, heterogeneous, and evolving. One potential solution is to resort to advanced machine learning techniques, in order to help manage the rise in data volumes and algorithm-driven applications. The recent success of deep learning underpins new and powerful tools that tackle problems in this space. In this paper, we bridge the gap between deep learning and mobile and wireless networking research, by presenting a comprehensive survey of the crossovers between the two areas. We first briefly introduce essential background and state-of-the-art in deep learning techniques with potential applications to networking. We then discuss several techniques and platforms that facilitate the efficient deployment of deep learning onto mobile systems. Subsequently, we provide an encyclopedic review of mobile and wireless networking research based on deep learning, which we categorize by different domains. Drawing from our experience, we discuss how to tailor deep learning to mobile environments. We complete this survey by pinpointing current challenges and open future directions for research.

/pdf/deep-learning-in-mobile-and-wireless-networking-a-survey-ct8cy2kuqi.pdf

Deep Learning in Mobile and Wireless Networking: A Survey

Objects. The ~ b s t rac t ~ b j ect forms the fundamental base class for the entire design and all other classes are derived from this base class. The Abstract Object class defines and characterizes all the essential properties every class in this 404 OBJECT-ORIENTED SIMULATION

Handbook of Simulation

Network lifetime has become the key characteristic for evaluating sensor networks in an application-specific way. Especially the availability of nodes, the sensor coverage, and the connectivity have been included in discussions on network lifetime. Even quality of service measures can be reduced to lifetime considerations. A great number of algorithms and methods were proposed to increase the lifetime of a sensor network—while their evaluations were always based on a particular definition of network lifetime. Motivated by the great differences in existing definitions of sensor network lifetime that are used in relevant publications, we reviewed the state of the art in lifetime definitions, their differences, advantages, and limitations. This survey was the starting point for our work towards a generic definition of sensor network lifetime for use in analytic evaluations as well as in simulation models—focusing on a formal and concise definition of accumulated network lifetime and total network lifetime. Our definition incorporates the components of existing lifetime definitions, and introduces some additional measures. One new concept is the ability to express the service disruption tolerance of a network. Another new concept is the notion of time-integration: in many cases, it is sufficient if a requirement is fulfilled over a certain period of time, instead of at every point in time. In addition, we combine coverage and connectivity to form a single requirement called connected coverage. We show that connected coverage is different from requiring noncombined coverage and connectivity. Finally, our definition also supports the concept of graceful degradation by providing means of estimating the degree of compliance with the application requirements. We demonstrate the applicability of our definition based on the surveyed lifetime definitions as well as using some example scenarios to explain the various aspects influencing sensor network lifetime.

/pdf/on-the-lifetime-of-wireless-sensor-networks-59hdyqoqi3.pdf

On the lifetime of wireless sensor networks

Graphics processors evolve rapidly and promise to support power-efficient, cost, differentiated price-performance, and scalable high performance computing. MapReduce is a well-known distributed programming model to ease the development of applications for large-scale data processing on a large number of commodity CPUs. When compared to CPUs, GPUs are an order of magnitude faster in terms of computation power and memory bandwidth, but they are harder to program. Although several studies have implemented the MapReduce model on GPUs, most of them are based on the single GPU model and bounded by a GPU memory with inefficient atomic operations. This paper focuses on the development of MGMR, a standalone MapReduce system that utilizes multiple GPUs to manage large-scale data processing beyond the GPU memory limitation, and also to eliminate serial atomic operations. Experimental results have demonstrated the effectiveness of MGMR in handling large data sets.

Accelerating MapReduce framework on multi-GPU systems

Configuration overhead is a major performance bottleneck of the partial reconfiguration process. In this paper, we propose a combination of two techniques to minimize the partial reconfiguration performance overhead. First, we design and implement fully streaming DMA engines to achieve a near perfect configuration throughput. Second, we exploit the configuration data redundancy through Run-Length Encoding to compress the configuration bitstreams, and we implement an intelligent ICAP (Internal Configuration Access Port) controller to perform decompression at runtime. The results show that our design achieve an effective configuration data transfer throughput that well surpasses the upper bound of data transfer throughput, 400 Mbytes/s. Specifically, our fully stream DMA engines reduce the configuration time from the range of seconds to the range of milliseconds, a more than 1000-fold improvement. In addition, our simple compression scheme achieves significant reduction of bitstream size and results in a decompression circuit with negligible hardware overhead.

Minimizing the runtime partial reconfiguration overheads in reconfigurable systems

Programming massively-parallel machine is a daunting task for any human programmer and parallelization may even be impossible for any compiler. Instead, the functional programming paradigm may prove to be an ideal solution by providing an implicitly parallel interface to the programmer. We describe here the Sisal project (Stream and Iteration in a Single Assignment Language) and its goal to provide a general-purpose user interface for a wide range of parallel processing platforms.

The Sisal project: real world functional programming

Simultaneous Multi-Threading (SMT) is a hardware technique that increases processor throughput by issuing instructions simultaneously from multiple threads. However, while SMT can be added to an existing microarchitecture with relatively low overhead, this additional chip area could be used for other resources such as more functional units, larger caches or better branch predictors. How large is the SMT overhead, and at what point does SMT no longer pay off compared to adding other architecture features? This paper evaluates the silicon overhead of SMT by performing a transistor/interconnect level analysis of the layout. We discuss micro-architecture issues that impact SMT implementations, and show how the Instruction Set Architecture (ISA) and microarchitecture can have a large effect on the SMT overhead and performance. Results show that SMT yields large performance gains with small to moderate area overhead.

Quantifying the SMT layout overhead-does SMT pull its weight?

This paper presents a cooperative heterogeneous computing framework which enables the efficient utilization of available computing resources of host CPU cores for CUDA kernels, which are designed to run only on GPU. The proposed system exploits at runtime the coarse-grain thread-level parallelism across CPU and GPU, without any source recompilation. To this end, three features including a work distribution module, a transparent memory space, and a global scheduling queue are described in this paper. With a completely automatic runtime workload distribution, the proposed framework achieves speedups as high as 3.08 compared to the baseline GPU-only processing.

/pdf/cooperative-heterogeneous-computing-for-parallel-processing-1qvv6tr7up.pdf

Jean-Luc Gaudiot

Papers

Accelerating MapReduce framework on multi-GPU systems

Minimizing the runtime partial reconfiguration overheads in reconfigurable systems

The Sisal project: real world functional programming

Quantifying the SMT layout overhead-does SMT pull its weight?

Cooperative heterogeneous computing for parallel processing on CPU/GPU hybrids