The objective of this paper is to give a comprehensive introduction to applied cryptography with an engineer or computer scientist in mind. The emphasis is on the knowledge needed to create practical systems which supports integrity, confidentiality, or authenticity. Topics covered includes an introduction to the concepts in cryptography, attacks against cryptographic systems, key use and handling, random bit generation, encryption modes, and message authentication codes. Recommendations on algorithms and further reading is given in the end of the paper. This paper should make the reader able to build, understand and evaluate system descriptions and designs based on the cryptographic components described in the paper.

[서평]「Applied Cryptography」

We review a model of computation used in industrial practice in signal processing software environments and experimentally and other contexts. We give this model the name "dataflow process networks," and study its formal properties as well as its utility as a basis for programming language design. Variants of this model are used in commercial visual programming systems such as SPW from the Alta Group of Cadence (formerly Comdisco Systems), COSSAP from Synopsys (formerly Cadis), the DSP Station from Mentor Graphics, and Hypersignal from Hyperception. They are also used in research software such as Khoros from the University of New Mexico and Ptolemy from the University of California at Berkeley, among many others. Dataflow process networks are shown to be a special case of Kahn process networks, a model of computation where a number of concurrent processes communicate through unidirectional FIFO channels, where writes to the channel are nonblocking, and reads are blocking. In dataflow process networks, each process consists of repeated "firings" of a dataflow "actor." An actor defines a (often functional) quantum of computation. By dividing processes into actor firings, the considerable overhead of context switching incurred in most implementations of Kahn process networks is avoided. We relate dataflow process networks to other dataflow models, including those used in dataflow machines, such as static dataflow and the tagged-token model. We also relate dataflow process networks to functional languages such as Haskell, and show that modern language concepts such as higher-order functions and polymorphism can be used effectively in dataflow process networks. A number of programming examples using a visual syntax are given. >

/pdf/dataflow-process-networks-3mdwy0uhx2.pdf

Dataflow process networks

The rapid uptake of mobile devices and the rising popularity of mobile applications and services pose unprecedented demands on mobile and wireless networking infrastructure. Upcoming 5G systems are evolving to support exploding mobile traffic volumes, real-time extraction of fine-grained analytics, and agile management of network resources, so as to maximize user experience. Fulfilling these tasks is challenging, as mobile environments are increasingly complex, heterogeneous, and evolving. One potential solution is to resort to advanced machine learning techniques, in order to help manage the rise in data volumes and algorithm-driven applications. The recent success of deep learning underpins new and powerful tools that tackle problems in this space. In this paper, we bridge the gap between deep learning and mobile and wireless networking research, by presenting a comprehensive survey of the crossovers between the two areas. We first briefly introduce essential background and state-of-the-art in deep learning techniques with potential applications to networking. We then discuss several techniques and platforms that facilitate the efficient deployment of deep learning onto mobile systems. Subsequently, we provide an encyclopedic review of mobile and wireless networking research based on deep learning, which we categorize by different domains. Drawing from our experience, we discuss how to tailor deep learning to mobile environments. We complete this survey by pinpointing current challenges and open future directions for research.

/pdf/deep-learning-in-mobile-and-wireless-networking-a-survey-ct8cy2kuqi.pdf

Deep Learning in Mobile and Wireless Networking: A Survey

Objects. The ~ b s t rac t ~ b j ect forms the fundamental base class for the entire design and all other classes are derived from this base class. The Abstract Object class defines and characterizes all the essential properties every class in this 404 OBJECT-ORIENTED SIMULATION

Handbook of Simulation

Network lifetime has become the key characteristic for evaluating sensor networks in an application-specific way. Especially the availability of nodes, the sensor coverage, and the connectivity have been included in discussions on network lifetime. Even quality of service measures can be reduced to lifetime considerations. A great number of algorithms and methods were proposed to increase the lifetime of a sensor network—while their evaluations were always based on a particular definition of network lifetime. Motivated by the great differences in existing definitions of sensor network lifetime that are used in relevant publications, we reviewed the state of the art in lifetime definitions, their differences, advantages, and limitations. This survey was the starting point for our work towards a generic definition of sensor network lifetime for use in analytic evaluations as well as in simulation models—focusing on a formal and concise definition of accumulated network lifetime and total network lifetime. Our definition incorporates the components of existing lifetime definitions, and introduces some additional measures. One new concept is the ability to express the service disruption tolerance of a network. Another new concept is the notion of time-integration: in many cases, it is sufficient if a requirement is fulfilled over a certain period of time, instead of at every point in time. In addition, we combine coverage and connectivity to form a single requirement called connected coverage. We show that connected coverage is different from requiring noncombined coverage and connectivity. Finally, our definition also supports the concept of graceful degradation by providing means of estimating the degree of compliance with the application requirements. We demonstrate the applicability of our definition based on the surveyed lifetime definitions as well as using some example scenarios to explain the various aspects influencing sensor network lifetime.

/pdf/on-the-lifetime-of-wireless-sensor-networks-59hdyqoqi3.pdf

On the lifetime of wireless sensor networks

Multimedia system-on-a-chip (SoC) platform designs nowadays are facing some conflicting issues regarding product development. One is induced by increasing design complexity and another is induced by decreasing time-to-market. Hence, designers are seeking a more efficient and reliable methodology in order to design complex multi-million gate SoC under such harsh conditions. In particular, the complexity of a generic pin control block in multimedia SoC which implements input/output (I/O) paths for off-chip communication has increased exponentially in recent years. Accordingly, the possibility of introducing human errors in designing such block has grown. Operation of generic-pin control block needs to be validated with a top-level RTL from the early stages of design, which correctly checks full-chip interface. However, generic-pin control block has inherent several design issues since function registers and multi-I/O paths are usually fixed in the relatively late stages of design. Also, the role of a generic pin control block that shares limited pins causes frequent changes in pin assignment. Therefore, current design approaches of a generic pin control block are no longer adequate to meet the challenges of design productivity, design reusability, and shorter time-to-market for design. And, this results in many possible human errors when using a traditional RTL description. As a response to this problem, this paper presents a design automation based approach to reduce the possibility of human errors. In the case study presented, we succeeded in auto-generating a generic pin control block in multimedia SoC platforms which has more than 300 general purpose I/O interfaces including both input and output, as well as 900 PAD pins. Ultimately, we reduced the amount of manual description for generating a generic pin control block by a whopping 97 %.

Design of configurable I/O pin control block for improving reusability in multimedia SoC platforms

Speculative pre-execution is a promising prefetching technique which uses an auxiliary assisting thread in addition to the main program flow. A prefetching thread (p-thread), which contains the future probable cache miss instructions and backward slice, can run on the spare hardware context for data prefetching. Recently, various forms of speculative pre-execution have been developed, including hardware-based and software-based approaches. The hardware-based approach has the advantage of using runtime information dynamically. However, it requires a complex implementation and also lacks global information such as data and control flow. On the other hand, the software-oriented approach cannot cope with dynamic events and imposes additional software overhead As a compromise, this paper introduces a hybrid model enhanced with novel compiler support for the dynamic pre-execution of a p-thread.

Compiler support for dynamic speculative pre-execution

BLAST is a widely used tool to search for similarities in protein and DNA sequences. However, the kernels of BLAST are not efficiently supported by general-purpose processors because of the special computational requirements of the kernels. In this paper, we propose an efficient PIM (Processor-In-Memory) architecture to effectively execute the kernels of BLAST. We propose not only to reduce the memory latencies and increase the memory bandwidth but also to execute the operations inside the memory where the data are located. We also propose to execute the operations in parallel by dividing the memory into small segments and by having each of these segments executes operations concurrently. Our simulation results show that our computing paradigm provides a 242x performance improvement for the executions of the kernels and a 12x performance improvement for the overall execution of BLAST.

An efficient PIM (Processor-In-Memory) architecture for BLAST

The sections in this article are


1
Programming Languages for Data-Driven Execution

2
Data-Flow Architectures

3
Multithreaded Architectures

4
Summary

Data-Flow and Multithreaded Architectures

One major obstacle faced by designers when entering the multicore era is how to harness the massive computing power which these cores provide. Since Instructional-Level Parallelism (ILP) is inherently limited, one single thread is not capable of efficiently utilizing the resource of a single core. Hence, Simultaneous MultiThreading (SMT) microarchitecture can be introduced in an effort to achieve improved system resource utilization and a correspondingly higher instruction throughput through the exploitation of Thread-Level Parallelism (TLP) as well as ILP. However, when multiple threads execute concurrently in a single core, they automatically compete for system resources. Our research shows that, without control over the number of entries each thread can occupy in system resources like instruction fetch queue and/or reorder buffer, a scenario called "mutual-hindrance" execution takes place. Conversely, introducing active resource sharing control mechanisms causes the opposite situation ("mutual-benefit" execution), with a possible significant performance improvement and lower cache miss frequency. This demonstrates that active resource sharing control is essential for future multicore multithreading microprocessor design.

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Jean-Luc Gaudiot

Papers

Design of configurable I/O pin control block for improving reusability in multimedia SoC platforms

Compiler support for dynamic speculative pre-execution

An efficient PIM (Processor-In-Memory) architecture for BLAST

Data-Flow and Multithreaded Architectures

The Impact of Resource Sharing Control on the Design of Multicore Processors