Showing papers by "Jean-Michel Portal published in 2012"

RRAM-based FPGA for "normally off, instantly on" applications

Abstract: "Normally off, instantly on" applications are becoming common in our environment. They range from healthcare to video surveillance. As the number of applications and their associated performance requirements grow rapidly, more and more powerful, flexible and power efficient computing units are necessary. In such a context, Field Programmable Gate Arrays (FPGA) architectures present a good trade-off between performance and flexibility. However, they consume high static power and can hardly be associated with power gating techniques due to their long context restoring phase. In this paper, we propose to integrate non-volatile resistive memories in configuration cells in order to instantly restore the FPGA context. We then show that if the circuit is in 'ON' state for less than 42% of time, non-volatile FPGA starts saving energy compared to classical FPGA. Finally, for a typical application with only 1% of time spent in 'ON' state, the energy gain reaches 50%.

Bipolar ReRAM Based non-volatile flip-flops for low-power architectures

Abstract: Resistive Random Access Memories (ReRAMs) fabricated in the back-end-of-line are a promising breakthrough for including permanent retention mechanisms in embedded systems. This low-cost solution opens the way to advanced power management schemes. In this paper, we propose novel design architecture of a non-volatile flip-flop based on Bipolar ReRAMs (Bi-RNVFF). Compared to state-of-the-art Data-Retention flip-flop (with Balloon latch), the proposed design is 25% smaller due to 6T structure compared to the 8T structure of Data-Retention flip-flop. Moreover, being non-volatile, the proposed architecture exhibits a zero leakage compared to a Data-Retention Flip-Flop, which consumes ∼3.2µW in sleep mode (leakage) for a 10K Flip-Flop design implemented in 22nm FDSOI technology. Our simulation results show that Bi-RNVFF is a true alternative for future “Power-on, Power-off” application adding Non-Volatility without significant burdening of the existing architectures.

Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications

Abstract: In this paper, we propose a new architecture of non-volatile Flip-Flop based on ReRAM unipolar resistive memory element (RNVFF). This architecture is proposed in the context of power-down applications. Flip-Flop content is saved into ReRAM memory cell before power-down and restored after power-up. To simulate such a structure a compact model of unipolar ReRAM was developed and calibrated on best in class literature data. The architecture of the RNVFF, based on the insertion of a non-volatile memory block before a master-slave Flip-Flop, is detailed. The save and restore processes are described from the succession of four operating modes (normal, save, read, reset) needed by the save and restore processes. Finally, the structure is fully validated through electrical simulations, when the data to save is either ‘0’ or ‘1’.

Test structures for interdie variations monitoring in presence of statistical random variability

Abstract: We study the limitations of single transistor test structures for Process Variations monitoring in presence of statistical random variability, and compare them with transistor array structures in 45 CMOS technology. By optimizing transistor array design considering statistical variability, layout effects, and interconnect parasitics, we first estimate and then verify on silicon that x5 reduction of statistical variability and excellent correlation with ring oscillator frequency that can be reached for array structure. Transistor arrays are demonstrated to be well suited for monitoring impact of process variations, whether it is die-to-die, or wafer-to-wafer.

PSP Based DCG-FGT Transistor Model Including Characterization Procedure on Dummy Cell

Abstract: A new DCG-FGT (dual-control-gate floating-gate transistor) transistor model for static and transient simulations is presented. The PSP MOS (metal-oxide-semiconductor) description is used as a basis for the formulation of the conduction channel behavior. The floating gate potential is implicitly computed with an added charge neutrality relation that ensures a good convergence. The model is running under electrical simulator (ELDO) and is characterized thanks to ICCAP (integrated circuit characterization and analysis program) software. It has been validated on an advanced STMicroelectronics technology. The final objective of this work is to provide an accurate and scalable model available in design framework. This device which is derived from a flash memory cell offers many possibilities for circuit design.