International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Method for fabrication of a semiconductor device and structure

The existence of reversible resistance switching (RS) behaviors induced by electric stimulus has been known for some time, and these intriguing physical phenomena have been observed in numerous materials, including oxides. As conventional charge-based random access memory is expected to face a size limit in the near future, a surge of renewed interest has been developed in RS phenomena for possible applications in small nonvolatile memory devices called resistance random access memory (RRAM). Of particular interest is unipolar RS, which shows the RS at two values of applied voltage of the same polarity. The unipolar RS exhibits a much larger resistance change than other RS phenomena, and this greatly simplifies the process of reading the memory state. When fabricated with oxide p-n diodes, memory cells using unipolar RS can be stacked vertically, which has the potential for dramatically increasing memory density. Therefore, unipolar RRAM may be a good candidate for multi-stacked, high density, nonvolatile memory. The most important scientific and technical issues concerning unipolar RS are how it works and the identification of its controlling parameters. Some studies have reported that unipolar RS comes from a homogeneous/inhomogeneous transition of current distribution, while others maintain that it comes from the formation and rupture of conducting filaments. Even with recent extensive studies on unipolar RS, its basic origin is still far from being understood. In addition, no model exists that actually explains how the reversible switching can occur at two values of applied voltage. This lack of a quantitative model poses a major barrier for unipolar RRAM applications. In this study, we describe RS behavior in polycrystalline TiO2 film. To explain the basic mechanism of unipolar RS behavior, we propose a new percolation model based on a network of ‘‘circuit breakers’’ with two switchable metastable states. The random circuit breaker (RCB) network model can explain the long-standing material issue of how unipolar RS occurs. This simple percolation model is different from the conventional percolation models, which have dealt only with static or irreversible dynamic processes. In addition, the RCB network model provides an indication of how to overcome the substantial distribution of switching voltages, which is currently considered the most serious obstacle to practical unipolar RRAM applications. The unipolar RS phenomenon can be explained by the current (I)-voltage (V) curves in Figure 1a, which are derived from measurements of our polycrystalline TiO2 thin capacitors. At the pristine state (green dot), they are in an insulating state. As the external voltage Vext increases from zero and reaches a threshold voltage Vforming, a sudden increase occurs in the current. If the current is not limited to a certain value, here called the compliance current Icomp, the TiO2 capacitor would experience a dielectric breakdown and be destroyed. However, [*] Prof. T. W. Noh, S. C. Chae, S. B. Lee, S. H Chang, Dr. C. Liu ReCOE & FPRD, Department of Physics and Astronomy Seoul National University Seoul 151-747 (Korea) E-mail: twnoh@snu.ac.kr

Random circuit breaker network model for unipolar resistance switching (Advanced Materials (2008) 20 (1154))

Various critical issues related with 3-D stacked nand Flash memory are examined in this paper. Our single-crystalline STacked ARray (STAR) has many advantages such as better scalability, possibility of single-crystal channel, less sensitivity to 3-D interference, stable virtual source/drain characteristic, and more extendability over other stacked structures. With STAR, we proposed a unit 3-D structure, i.e., “building.” Then, using this new component, 3-D block and full chip architecture are successfully designed. For the first time, the structure and operation methods of the “full” array are considered. The fully designed 3-D nand Flash architecture will be the novel solution of reliable 3-D stacked nand Flash memory for terabit density.

Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

Example embodiments disclose a semiconductor device using resistive memory material layers and a method of driving the semiconductor device. The semiconductor device includes a plurality of memory cells. At least one memory cell includes a uni-polar variable resistor and a bi-polar variable resistor connected in series and configured to switch between low resistance states and high resistance states, respectively, according to an applied voltage.

Semiconductor devices and methods of driving the same

The present invention provides a method of eliminating or covering a defect source in a wafer edge region for semiconductor fabrication. During the etching process of a sacrificial oxide layer for storage node openings, the sacrificial oxide layer has a rumple topology in the wafer edge region due to etching non-uniformity of a photoresist layer formed on the sacrificial oxide layer. Subsequent deposition of a conductive layer and planarization etching, the conductive layer undesirably remains at the wafer edge region as a defect source. Such conductive contaminant particles dislodge, causing many problems in the wafer main region. The present invention removes such a defect source via two methods. One is to directly remove the defect source using a photoresist pattern exposing thereof. The other is to fix the defect source in place in the wafer edge region by protecting thereof by a photoresist pattern during subsequent cleaning processes.

Method of processing a defect source at a wafer edge region in a semiconductor manufacturing

We firstly propose a novel U-shape resistive cell structure which is the best fit for generating low power resistive random access memory (RRAM) with forming-less process. We find that irregular resistive switching behavior in the initial transition and the characteristics associated with it. Controlling the conducting filament (CF) dimension and deposition orientation of resistive material are expected to reduce the distribution and forming voltage, which enables low power RRAM to be feasible without forming state. Simple fabrication flow and device performances are also evaluated in the aspect of forming-less process. Numerical simulation is performed using random circuit breaker model (RCB) to confirm the proposed structure.

Novel U-Shape Resistive Random Access Memory Structure for Improving Resistive Switching Characteristics

A device isolation region is formed, delimiting an active region in a substrate. A word line is formed, extending across the active region and the device isolation region and buried therein. A bit line is formed crossing the word line on the substrate. A channel is formed adjacent the word line, the channel having a retrograde doping profile having a doping concentration that increases away from a top surface of the active region. Formation of the channel includes performing a field ion implantation in the active region having a projected range near a bottom of the device isolation region.

Jeong-Hoon Oh

Papers

Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

Semiconductor devices and methods of driving the same

Method of processing a defect source at a wafer edge region in a semiconductor manufacturing

Novel U-Shape Resistive Random Access Memory Structure for Improving Resistive Switching Characteristics

Semiconductor devices having channels with retrograde doping profile