A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Method for fabrication of a semiconductor device and structure

Issues in the circuitry, integration, and material properties of the two-dimensional (2D) and three-dimensional (3D) crossbar array (CBA)-type resistance switching memories are described. Two important quantitative guidelines for the memory integration are provided with respect to the required numbers of signal wires and sneak current paths. The advantage of 3D CBAs over 2D CBAs (i.e., the decrease in effect memory cell size) can be exploited only under certain limited conditions due to the increased area and layout complexity of the periphery circuits. The sneak current problem can be mitigated by the adoption of different voltage application schemes and various selection devices. These have critical correlations, however, and depend on the involved types of resistance switching memory. The problem is quantitatively dealt with using the generalized equation for the overall resistance of the parasitic current paths. Atomic layer deposition is discussed in detail as the most feasible fabrication process of 3D CBAs because it can provide the device with the necessary conformality and atomic-level accuracy in thickness control. Other subsidiary issues related to the line resistance, maximum available current, and fabrication technologies are also reviewed. Finally, a summary and outlook on various other applications of 3D CBAs are provided.

A Review of Three-Dimensional Resistive Switching Cross-Bar Array Memories from the Integration and Materials Property Points of View

An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.

3D semiconductor device and structure

Various critical issues related with 3-D stacked nand Flash memory are examined in this paper. Our single-crystalline STacked ARray (STAR) has many advantages such as better scalability, possibility of single-crystal channel, less sensitivity to 3-D interference, stable virtual source/drain characteristic, and more extendability over other stacked structures. With STAR, we proposed a unit 3-D structure, i.e., “building.” Then, using this new component, 3-D block and full chip architecture are successfully designed. For the first time, the structure and operation methods of the “full” array are considered. The fully designed 3-D nand Flash architecture will be the novel solution of reliable 3-D stacked nand Flash memory for terabit density.

Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

This letter describes 3-D NAND flash memory architecture having four-level stacked single-crystalline silicon nanowire channels. Previously, we designed 3-D NAND flash memory architecture based on single-crystalline channel stacked array (CSTAR). In this letter, CSTAR NAND flash memory is fabricated and its operations are verified. Successful memory operations of each stacked array of CSTAR including program/erase, retention, and endurance performances are demonstrated.

Three-Dimensional NAND Flash Memory Based on Single-Crystalline Channel Stacked Array

In this paper, the channel stacked array (CSTAR) NAND flash memory with layer selection by multi-level operation (LSM) of string select transistor (SST) is proposed and investigated to solve problems of conventional channel stacked array. In case of LSM architecture, the stacked layers can be distinguished by combinations of multi-level states of SST and string select line (SSL) bias. Due to the layer selection performed by the bias of SSL, the placement of bit lines and word lines is similar to the conventional planar structure, and proposed CSTAR with LSM has no island-type SSLs. As a result of the advantages of the proposed architecture, various issues of conventional channel stacked NAND flash memory array can be solved.

Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM)

In this paper, we present a detailed study of the physical dynamics of the program/erase (P/E) operations in nitride-based NAND-type charge trapping silicon–oxide–nitride–oxide–silicon (SONOS) flash memories. By calculating the internal oxide fields, tunneling currents, and trapping charges, we evaluated the simple charge trapping mechanism. We calculated transient P/E threshold voltage (VT) shift considering the ONO fields and tunneling currents. All the parameters were obtained using totally physics-based equations with no fitting parameters or optimization steps. The results show conventional NAND SONOS flash memory P/E characteristics in the Fowler–Nordheim (FN) operation regime. Also, these P/E simulation results agree with the measurement data of 30×70 nm2 (L×W) SONOS flash memory devices that have 2.3/12/4.5 and 3/9/7 nm ONO stack layers. This model fully accounts for the VT shift as a function of the applied gate voltage, transient time, and thicknesses of silicon oxide and silicon nitride layers, which can be used for optimizing the ONO thicknesses and the parameters for improving performance.

https://iopscience.iop.org/article/10.1143/JJAP.49.084301/pdf

Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories

Junctionless field-effect transistor (JLFET) is an attractive electronic device due to its simpler process architecture without concerning about thermal budgets in forming source and drain (S/D) junctions JLFETs with silicon (Si) channel have been explored in many aspects [1–2], but they are not cost-effective since they need expensive silicon-on-insulator (SOI) substrate for electrical isolation of a device In this work, a Si-compatible bulk-type compound JLFET is introduced and characterized by two-dimensional (2D) simulation [3] Compound JLFET can be used as a core element in the driving circuits for integrated biosensors and photonic systems based on the compound semiconductors Fig 1(a) and (b) compare the material compositions of the conventional and the proposed JLFETs The channel material is n+ gallium arsenide (GaAs) grown on Si substrate with a thick enough buffer layer of p+ germanium (Ge) for an n-type FET The GaAs channel is epitaxially grown on Ge buffer layer with little lattice mismatch (Fig 2) Also, GaAs and Ge have a large energy bandgap offset, which enables a self-isolation by effectively blocking leakage paths between the channel and substrate at any operation conditions The simulated energy band diagrams with inserted schematics under various conditions are shown in Fig 3(a) through (d) This genuine feature of self-isolation gets the device evolved into a vertical structure (which is suitable for surrounding gate) with one of the GaAs S/D junctions grown on Ge buffer The gate oxide thickness (T ox ), physical gate length (L G ), and channel thickness (T ch ) of the simulated device in Fig 3 were 1 nm, 40 nm, and 20 nm, respectively The buffer layer and channel doping concentrations (N BF , N ch ) were N BF = 3×1017 cm−3 and N ch = 1×1018 cm−3 A metal gate with workfunction of 433 eV was used throughout the works It is confirmed that leakages by band-to-band tunneling of Ge valence electrons with a high drain voltage (V DS ) and by hole current with a negative gate voltage (V GS ) are effectively blocked by the bandgap offsets between n+ GaAs and p+ Ge The doping concentrations (for buffer layer and channel) and the channel thickness were controlled to examine their effects on device performance Fig 4(a) through (c) shows the I D −V GS curves and direct-current (DC) parameters of the proposed JLFET with different N BF 's at T ch = 20 nm and N ch = 1×1018 cm−3 Threshold voltages (V th 's) were extracted at a constant drain current of I D = 10−6 A/μm in the saturation region, V GS = V DS = 10 V Higher N BF steepens the subthreshold slope (SS) but may have an upper limit near 3×1017 cm−3 for on-state current (I on ) no less than 100 μA/μm reducing the mobility degradation [4] The effects of N ch are demonstrated in Fig 5(a) through (c) (N BF = 3×1017 cm−3, T ch = 20 nm) I on shows a monotonic increase with N ch but it is noticeable that there is an optimum value in I on /I off ratio near N ch = 1×1018 cm−3 The effects of T ch were also investigated (Fig 6) Although higher I on is expected as T ch gets thickner, the switching characteristics are degraded T ch can be optimized in terms of SS and I on /I off , which leads to 20 nm as the appropriate value

Se Hwan Park

Papers

Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

Three-Dimensional NAND Flash Memory Based on Single-Crystalline Channel Stacked Array

Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM)

Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories

Silicon-compatible bulk-type compound junctionless field-effect transistor