Progress in the production and modification of PVDF membranes

Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers.

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Review: Semiconductor Piezoresistance for Microsystems

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

A detailed theoretical picture is given for the physics of strain effects in bulk semiconductors and surface Si, Ge, and III–V channel metal-oxide-semiconductor field-effect transistors. For the technologically important in-plane biaxial and longitudinal uniaxial stress, changes in energy band splitting and warping, effective mass, and scattering are investigated by symmetry, tight-binding, and k⋅p methods. The results show both types of stress split the Si conduction band while only longitudinal uniaxial stress along ⟨110⟩ splits the Ge conduction band. The longitudinal uniaxial stress warps the conduction band in all semiconductors. The physics of the strain altered valence bands for Si, Ge, and III–V semiconductors are shown to be similar although the strain enhancement of hole mobility is largest for longitudinal uniaxial compression in ⟨110⟩ channel devices and channel materials with substantial differences between heavy and light hole masses such as Ge and GaAs. Furthermore, for all these materials,...

Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors

Large differences in the experimentally observed strain-induced threshold-voltage shifts for uniaxial and biaxial tensile-stressed silicon (Si) n-channel MOSFETs are explained and quantified. Using the deformation potential theory, key quantities that affect threshold-voltage (electron affinity, bandgap, and valence band density of states) are expressed as a function of strain. The calculated threshold-voltage shift is in agreement with uniaxial wafer bending and published biaxial strained-Si on relaxed-Si/sub 1-x/Ge/sub x/ experimental data , and explains the technologically important observation of a significantly larger (>4x) threshold-voltage shift for biaxial relative to uniaxial stressed MOSFETs. The large threshold shift for biaxial stress is shown to result from the stress-induced change in the Si channel electron affinity and bandgap. The small threshold-voltage shift for uniaxial process tensile stress is shown to result from the n/sup +/ poly-Si gate in addition to the Si channel being strained and significantly less bandgap narrowing.

Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs

For both n and pMOSFETs, this paper confirms via controlled wafer bending experiments and physical modeling the superiority of uniaxial over biaxial stressed Si and Ge MOSFETs. For uniaxial stressed p-MOSFETs, valence band warping creates favorable in and out-of-plane conductivity effective masses resulting in significantly larger hole mobility enhancement at low strain and high vertical field. For process-induced uniaxial stressed n-MOSFETs, a significant performance advantage results from a smaller threshold voltage shift due to less bandgap narrowing and the gate also being strained.

Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs

Changes in the direct gate tunneling current are measured for strained p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) on (100) wafers for uniaxial and biaxial stress. Decreases/increases in the gate tunneling current for various stresses primarily result from repopulation into a subband with a larger/smaller out-of-plane effective mass. Strain-induced changes in the valence band offset between Si and SiO2 are also important but play a secondary role. Hole tunneling current is found to decrease for biaxial and uniaxial compressive stress and increase for biaxial tensile stress. The hole tunneling data is modeled using k∙p self-consistent solution to Poisson and Schrodinger’s equation, and a transfer matrix method.

Strain-induced changes in the gate tunneling currents in p-channel metal–oxide–semiconductor field-effect transistors

An experimental method to determine both the hydrostatic and shear deformation potential constants is introduced. The technique is based on the change in the gate tunneling currents of Si-metal oxide semiconductor field effect transistors (MOSFETs) under externally applied mechanical stress and has been applied to industrial n-type MOSFETs. The conduction band hydrostatic and shear deformation potential constants (Ξd and Ξu) are extracted to be 1.0±0.1 and 9.6±1.0eV, respectively, which is consistent with recent theoretical works.

Measurement of conduction band deformation potential constants using gate direct tunneling current in n-type metal oxide semiconductor field effect transistors under mechanical stress

Strain altered electron gate tunneling current is measured for germanium (Ge) metal–oxide–semiconductor devices with HfO2 gate dielectric. Uniaxial mechanical stress is applied using four-point wafer bending along [100] and [110] directions to extract both dilation and shear deformation potential constants of Ge. Least-squares fit to the experimental data results in Ξd and Ξu of −4.3±0.3 and 16.5±0.5 eV, respectively, which agree with theoretical calculations. The dominant mechanism for the strain altered electron gate tunneling current is a strain-induced change in the conduction band offset between Ge and HfO2. Tensile stress reduces the offset and increases the gate tunneling current for Ge while the opposite occurs for Si.

Ji-Song Lim

Papers

Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs

Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs

Strain-induced changes in the gate tunneling currents in p-channel metal–oxide–semiconductor field-effect transistors

Measurement of conduction band deformation potential constants using gate direct tunneling current in n-type metal oxide semiconductor field effect transistors under mechanical stress

Mechanical stress altered electron gate tunneling current and extraction of conduction band deformation potentials for germanium