Damascene Cu electroplating for on-chip metallization, which we conceived and developed in the early 1990s, has been central to IBM's Cu chip interconnection technology. We review here the challenges of filling trenches and vias with Cu without creating a void or seam, and the discovery that electrodeposition can be engineered to give filling performance significantly better than that achievable with conformal step coverage. This attribute of superconformal deposition, which we call superfilling, and its relation to plating additives are discussed, and we present a numerical model that represents the shape-change behavior of this system.

Damascene Copper electroplating for chip interconnections

Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

The authors survey the current state of phase change memory (PCM), a nonvolatile solid-state memory technology built around the large electrical contrast between the highly resistive amorphous and highly conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance, and yield characteristics. They introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. Challenges for the technology are addressed, including the design of PCM cells for low reset current, the need to control device-to-device variability, and undesirable changes in the phase change material that c...

Phase change memory technology

The design and fabrication of three-dimensional multifunctional architectures from the appropriate nanoscale building blocks, including the strategic use of void space and deliberate disorder as design components, permits a re-examination of devices that produce or store energy as discussed in this critical review. The appropriate electronic, ionic, and electrochemical requirements for such devices may now be assembled into nanoarchitectures on the bench-top through the synthesis of low density, ultraporous nanoarchitectures that meld high surface area for heterogeneous reactions with a continuous, porous network for rapid molecular flux. Such nanoarchitectures amplify the nature of electrified interfaces and challenge the standard ways in which electrochemically active materials are both understood and used for energy storage. An architectural viewpoint provides a powerful metaphor to guide chemists and materials scientists in the design of energy-storing nanoarchitectures that depart from the hegemony of periodicity and order with the promise—and demonstration—of even higher performance (265 references).

Multifunctional 3D nanoarchitectures for energy storage and conversion.

Atomic layer deposition (ALD) has been studied for several decades now, but the interest in ALD of metal and nitride thin films has increased only recently, driven by the need for highly conformal nanoscale thin films in modern semiconductor device manufacturing technology. ALD is a very promising deposition technique with the ability to produce thin films with excellent conformality and compositional control with atomic scale dimensions. However, the applications of metals and nitrides ALD in semiconductor device processes require a deeper understanding about the underlying deposition process as well as the physical and electrical properties of the deposited films. This article reviews the current research efforts in ALD for metal and nitride films as well as their applications in modern semiconductor device fabrication.

Atomic layer deposition of metal and nitride thin films: Current research efforts and applications for semiconductor device processing

An electroplating cell includes a floor, ceiling, front wall, and back wall forming a box having first and second opposite open ends. A rack for supporting an article to be electroplated is removably positioned vertically to close the first open end and includes a thief laterally surrounding the article to define a cathode. An anode is positioned vertically to close the second open end, with the assembly defining a substantially closed, six-sided inner chamber for receiving an electrolyte therein for electroplating the article. The article and surrounding thief are coextensively aligned with the anode, with the floor, ceiling, front and back walls being effective for guiding electrical current flux between the cathode and the anode. In a preferred embodiment, the cell is disposed as an inner cell inside an outer cell substantially filled with the electrolyte, and a paddle is disposed inside the inner cell for agitating the electrolyte therein. The rack is removable and installable vertically upwardly which allows for automated handling thereof.

Vertical paddle plating cell

Agitation effects on electrodeposition have been systematically investigated using a rotating ring‐disk electrode. Alloy compositions and bath current efficiencies have been shown to vary widely over the range of plating current densities and rotation speeds used. An analysis of partial currents as a function of electrode potential has shown that the Fe deposition reaction is mass‐transport controlled at sufficient cathodic potentials, and that the diffusivity of the Fe2+ ion is the same for both the reduction to Fe0 and the oxidation to Fe3+. In agreement with the observations of Dahms and Croll, the Ni deposition reaction is inhibited when Fe is codeposited. This inhibition effect, manifest as a cathodic shift in the Ni polarization curve, increases in magnitude with increased agitation. The dependence of Ni inhibition on agitation is seen only under conditions at which Fe deposition is mass‐transfer influenced, which suggests that Ni inhibition is primarily dependent on the flux of Fe2+ to the electrode surface. The rate of hydrogen evolution during deposition shows the same dependence on potential and agitation as it does in a Ni2+‐ and Fe2+‐free bath on a substrate.

Electrodeposition of Nickel‐Iron Alloys I . Effect of Agitation

Apparatus for treating the surface of a substrate, the apparatus comprising a clamshell (32) mounted on a rotatable spindle (40). The clamshell comprises a cone (34), a cup (36) and a flange (48). The flange (48) has apertures (50) which are adjacent the substrate or wafer (38) allowing gas bubbles entrapped on the substrate surface to readily escape.

John Owen Dukovic

Papers

Damascene Copper electroplating for chip interconnections

Damascene copper electroplating for chip interconnections

Vertical paddle plating cell

Electrodeposition of Nickel‐Iron Alloys I . Effect of Agitation

Electric potential shaping apparatus for holding a semiconductor wafer during electroplating