Kwong-Hon Wong

TL;DR: An electroplating cell includes a floor, ceiling, front wall, and back wall forming a box having first and second opposite open ends as mentioned in this paper, with a rack for supporting an article to be electroplated is removably positioned vertically to close the first open end and includes a thief laterally surrounding the article to define a cathode.

TL;DR: In this paper, a process for the fabrication of submicron interconnect structures for integrated circuit chips is described, where void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal.

TL;DR: In this paper, a process for the fabrication of submicron interconnect structures for integrated circuit chips is described, where void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal.

TL;DR: In this paper, the authors proposed an interconnect structure that exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above.

TL;DR: In this article, a seamless conductor without void can be obtained by electroplating Cu from a bath, usually employed for adhering Cu metal which comprises an adhing agent and which is flat, glossy, ductile and low stress.