We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

/pdf/all-digital-pll-and-transmitter-for-mobile-phones-2mf5fxyzjo.pdf

All-digital PLL and transmitter for mobile phones

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

https://users.ece.utexas.edu/~adnan/comm-08/bluetooth-jssc-04.pdf

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

This paper presents the design of a coarse-fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, similar to a coarse-fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time residue with a higher gain (>16) and larger range (>80 ps) than existing solutions do. However, adapting the conventional coarse-fine architecture from ADCs is not an appropriate solution for TDCs: input time cannot be stored, and the gain of a time amplifier (TA) cannot be controlled precisely. This paper proposes a new coarse-fine TDC architecture by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process. The measured DNL and INL are plusmn0.8 LSB and plusmn3 LSB, respectively, with a value of 1.25 ps per 1 LSB, while the standard deviation of output code for constant inputs remains below 1 LSB across the TDC range. Although the nonlinearity is larger than 1 LSB, using an INL lookup table or better matched delays in the coarse TDC delay chain will improve the linearity further.

A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue

After being the subject of speculation for many years, a software-defined radio receiver concept has emerged that is suitable for mobile handsets. A key step forward is the realization that in mobile handsets, it is enough to receive one channel with any bandwidth, situated in any band. Thus, the front-end can be tuned electronically. Taking a cue from a digital front-end, the receiver's flexible analog baseband samples the channel of interest at zero IF, and is followed by clock-programmable downsampling with embedded filtering. This gives a tunable selectivity that exceeds that of an RF prefilter, and a conversion rate that is low enough for A/D conversion at only milliwatts. The front-end consists of a wideband low noise amplifier and a mixer tunable by a wideband LO. A 90-nm CMOS prototype tunes 200 kHz to 20-MHz-wide channels located anywhere from 800 MHz to 6 GHz

The Path to the Software-Defined Radio Receiver

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

An RF receiver front-end for a GSM/GPRS radio system-on-chip in a 90 nm digital CMOS technology is presented The circuit consisting of low noise amplifier, transconductance amplifier and switching mixer, offers 325 dB dynamic range with digitally-configurable voltage gain of 40 dB down to 75 dB A series of decimation and discrete-time filtering follows the mixer and performs a highly-linear second-order low-pass filtering to reject close-in interferers The front-end gains can be configured with an automatic-gain-control to select an optimal setting to form a trade-off between noise figure and linearity and to compensate the process and temperature variations Even under the digital switching activity, noise figure at the 40 dB maximum gain is 18 dB and +50 dBm IIP/sub 2/ at the 34 dB gain The variation of the input matching versus multiple gains is less than 1 dB The circuit in total occupies 31 mm/sup 2/ The LNA, TA and mixer consume less than 153 mA at a supply voltage of 14 V

A GSM/GPRS receiver front-end with discrete-time filters in a 90 nm digital CMOS

A novel apparatus for and method of acquisition and tracking bank cooperation in a digitally controlled oscillator (DCO) within an all digital phase locked loop (ADPLL). The acquisition bits of the acquisition bank are used as an extension of the modulation range. The PLL and TX tuning data are broken up (i.e. apportioned) into acquisition components and tracking components. This permits the use of two different capacitor banks (i.e. the tracking and acquisition banks) for modulation rather than just a single capacitor bank as in the prior art schemes. Incorporating the tracking and acquisition bit varactors, the cooperation scheme of the present invention permits the re-centering of the tracking bank to handle natural frequency drift of the DCO and the widening of the modulation range.

Apparatus and method for acquisition and tracking bank cooperation in a digitally controlled oscillator

In this paper, we describe a new architecture of high-speed multibit /spl Sigma//spl Delta/ noise shaping for digital-to-frequency conversion (DFC) and digital-to-RF-amplitude conversion (DRAC). The DFC and DRAC are instrumental in performing phase modulation (PM) and amplitude modulation (AM) of an RF polar transmitter. Since current biasing and continuous-time analog filtering of a conventional transmit modulator are avoided in this all-digital architecture, it is amenable to large-scale integration in an SoC realized in a digital deep-submicron CMOS process. The approach is demonstrated in the first single-chip fully-compliant GSM/EDGE transceiver realized in 90-nm CMOS.

Sigma-delta noise shaping for digital-to-frequency and digital-to-RF-amplitude conversion

A novel method of estimating gain of a digitally-controlled oscillator (DCO) for wireless RF applications is proposed and demonstrated. By executing the calculation algorithm just-in-time at the beginning of every packet, the DCO gain can be conveniently tracked and compensated. Precise and timely knowledge of the DCO gain makes possible various predictive operations of a frequency synthesizer such as the two-point modulation method. This enables the employment of sophisticated and fully-digital frequency synthesizers capable of compensating for analog non-idealities. The demonstrator test chip has been fabricated in a digital 0.13 /spl mu/m CMOS process. The presented ideas have been incorporated in a fully-compliant Bluetooth transceiver.

Just-in-time gain estimation of an RF digitally-controlled oscillator

A novel testing mechanism operative to test large capacitor arrays such as those used in a digitally controlled crystal oscillator (DCXO). The invention is adapted for use in DCXO circuits that employ dynamic element matching in their array decoding circuits. The invention combines the use of DEM during regular operation of the DCXO with a testing technique that greatly reduces the number of tests required. The invention tests the capacitors in the array on a row by row, wherein all the capacitors in a row are tested lumped together and treated as a single entity, which results in significantly reduced testing time. This permits the measurement of significantly higher frequency deviations due to the larger capacitances associated with an entire row of capacitors being tested.

John Wallberg

Papers

A GSM/GPRS receiver front-end with discrete-time filters in a 90 nm digital CMOS

Apparatus and method for acquisition and tracking bank cooperation in a digitally controlled oscillator

Sigma-delta noise shaping for digital-to-frequency and digital-to-RF-amplitude conversion

Just-in-time gain estimation of an RF digitally-controlled oscillator

Built-in self test method for a digitally controlled crystal oscillator