C. Fernando

TL;DR: The first all-digital PLL and polar transmitter for mobile phones is presented, exploiting the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom.

TL;DR: A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time.

TL;DR: A novel simulation technique that uses an event-driven VHDL simulator to model phase noise behavior of an RF oscillator for wireless applications is proposed and demonstrated and has been successfully applied and validated in a Bluetooth transceiver integrated circuit fabricated in a digital 130-nm process.

TL;DR: A discrete-time receiver architecture for a wireless application is presented and analog signal processing concepts are used to directly sample the RF input at Nyquist rate.

TL;DR: The RF transceiver is built on the Digital RF Processor (DRP) technology, and the ADPLL-based transmitter uses a polar architecture with all-digital PM-FM and AM paths.