Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

Method for integrated circuit fabrication using pitch multiplication

Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures

Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

Pitch reduced patterns relative to photolithography features

https://chemistry.beloit.edu/classes/nanotech/sensors/mattoday13_11_28.pdf

Electrical nanogap devices for biosensing

The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. To form a pattern of pitch-multiplied spacers, a pattern of mandrels is first formed overlying a semiconductor substrate. Spacers are then formed on sidewalls of the mandrels by depositing a blanket layer of material over the mandrels and preferentially removing spacer material from horizontal surfaces. The mandrels are then selectively removed, leaving behind a pattern of freestanding spacers. The spacers comprise a material, such as polysilicon and amorphous silicon, known to increase in size upon being oxidized. The spacers are oxidized to grow them to a desired width. After reaching the desired width, the spacers can be used as a mask to pattern underlying layers and the substrate. Advantageously, because the spacers are grown by oxidation, thinner blanket layers can be deposited over the mandrels, thereby allowing the deposition of more conformal blanket layers and widening the process window for spacer formation.

Mask material conversion

We describe parallel processes for nanometer pattern generation on a wafer scale with resolution comparable to the best electron beam lithography. Sub-10 nm linewidth is defined by a sacrificial ultrathin film deposited by low pressure chemical vapor deposition (LPCVD), in a process similar to formation of gate sidewall spacers in CMOS processing. We further demonstrate a method called iterative spacer lithography (ISL), in which the process is repeated multiple times with alternating materials in order to multiply the pattern density. Silicon structures with sub-10 nm width fabricated by this process were used as a mold in nanoimprint lithography and lift-off patterning of sub-30 nm platinum nanowires for use in experiments on chemical catalysis. We also demonstrate a similar process called reversed spacer lithography (RSL) to form sub-10 nm fluid channels in poly-Si. This nanogap fluid channel device was used for label-free detection of DNA hybridization based on electrical sensing of dielectric changes...

Sublithographic nanofabrication technology for nanocatalysts and DNA chips

Nanogap electrodes-based dielectric spectroscopy is introduced to create ultrasensitive biomolecular sensors by minimizing the effects of electrode polarization. The electrode polarization is a major source of error in determining the impedance of biological samples in solution. The unwanted double layer impedance due to the electrode polarization impedance. is caused by the accumulation of ions on the surface of electrode. This effect becomes more dominant in low frequency region (< 1 kHz). In this paper we describe nanogap electrodes-based biomolecular measurements that can minimize electrode polarization effects since the double layers overlap and potential drop inside of the electrode gap can be reduced in nanoscale (<100 nm) electrode spacing.

Minimization of electrode polarization effect by nanogap electrodes for biosensor applications

Nanogap capacitors are fabricated for DNA hybridization detection. Without labeling, the nanogap capacitors on a chip can function as DNA microarray sensors. The difference in dielectric properties between single-stranded DNA and double-stranded DNA permits use of capacitance measurements to detect hybridization. To obtain high detection sensitivity, a 50 nm gap capacitor was fabricated using a Si-nanotechnology. To ensure proper measurement of DNA's dielectrical properties, the probe ssDNA was first immobilized onto the electrode surface using self-assembly monolayers and allowed to hybridize with the target ssDNA. The capacitance changes were measured for 35-mer homonucleotides. The self-assembly monolayer and DNA immobilization events were verified independently by contact angle measurement and FTIR. Capacitance values are measured at frequencies ranging from 75 kHz to 5 MHz, using 0 V DC bias and 25 m V AC signals. Approximately 9% change in capacitance was observed after DNA hybridization at 75 kHz.

/pdf/nanogap-capacitors-for-label-free-dna-analysis-1lyr0u28pl.pdf

Nanogap Capacitors for Label Free DNA Analysis

Sub-lithographic nanowires and nanogaps were fabricated by spacer lithography (size reduction technology), which is a parallel processes for nanometer pattern generation on a wafer scale with resolution comparable to the best electron beam lithography. Sub-10nm line width is defined by using a sacrificial ultrathin film deposited by low pressure chemical vapor deposition (LPCVD), in a process similar to formation of gate sidewall spacers in CMOS processing. Furthermore, a novel method called iterative spacer lithography (ISL) is demonstrated by alternating materials and repeating the spacer lithography multiple times in order to multiply the pattern density. Silicon structures with sub-10nm width fabricated by this process were used as a mold in nanoimprint lithography and lift-off patterning of sub-30nm platinum nanowires for use as model catalyst systems. A similar process called reversed spacer lithography (RSL) is demonstrated to form sub10nm nanogap device and fluid channels in poly-Si. This nanogap device provides a label-free tool for DNA hybridization detection based on measuring capacitance changes in the gap.

Sub-Lithographic Patterning Technology for Nanowire Model Catalysts and DNA Label-Free Hybridization Detection

A label-free dielectric detection of DNA hybridization with a nanogap junction is described. Nanogap junctions are fabricated with a novel spacer process technology and the change in capacitance of DNA within the nanogap after hybridization is measured. The 70% change of capacitance after hybridization is accomplished at 100 Hz for 10-5 mol/L concentrations of target DNA.

Joon Sung Lee

Papers

Sublithographic nanofabrication technology for nanocatalysts and DNA chips

Minimization of electrode polarization effect by nanogap electrodes for biosensor applications

Nanogap Capacitors for Label Free DNA Analysis

Sub-Lithographic Patterning Technology for Nanowire Model Catalysts and DNA Label-Free Hybridization Detection

Label-Free Dielectric Detection of DNA Hybridization with Nanogap Junctions