Showing papers by "José Monteiro published in 2010"

CentroidM: a centroid-based localization algorithm for mobile sensor networks

Abstract: In this paper, we present an adaptation of the well-known, range-free Centroid localization algorithm to deal with node mobility. This algorithm, which we call CentroidM, has the Centroid method as a stand. Positive features of the Centroid algorithm were kept while their limitations due to the dynamic characteristics of the network movement were mitigated. We consider a topology where a fraction of the nodes, called anchors, are static and are aware of their positions, while the remaining nodes are mobile. The proposed method splits the original sampling period of the Centroid algorithm into temporal windows in order to maintain a record of past information during movement. The selection of the anchor nodes is based on the received data within these temporal windows, allowing for the weighing of the anchors' coordinates. The method proved to increase the accuracy of the Centroid algorithm in static and mobile networks. The simulations were conducted under noisy environments and random mobility. Comparisons with the original algorithm show that our proposal achieves error reductions in the localization estimations up to 42% in the presence of movement and more than 30% for a static topology, leading to a significantly more accurate range-free localization process. Besides the concern regarding the accuracy of the method, the power consumption of the algorithm was addressed too. These benefits have increased 2.76 times the time spent by the CentroidM to run a localization process. However, simulation results showed it is possible to remove such overhead and still keep the achieved estimation gains near 10%.

An efficient low power multiple-value look-up table targeting quaternary FPGAs

Abstract: FPGA structures are widely used as they enable early time-to-market and reduced non-recurring engineering costs in comparison to ASIC designs. Interconnections play a crucial role in modern FPGAs, because they dominate delay, power and area. Multiple-valued logic allows the reduction of the number of interconnections in the circuit, hence can serve as a mean to effectively curtail the impact of interconnections. In this work we propose a new look-up table structure based on a lowpower high-speed quaternary voltage-mode device. The most important characteristics of the proposed architecture are that it is a voltage-mode structure, which allows reduced power consumption, and it is implemented with a standard CMOS technology. Our quaternary implementation overcomes previous proposed techniques with simple and efficient CMOS structures. Moreover, results show significant reductions on power consumption and timing in comparison to binary implementations with similar functionality.

Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications

Abstract: Although many efficient high-level algorithms have been proposed for the realization of Multiple Constant Multiplications (MCM) using the fewest number of addition and subtraction operations, they do not consider the low-level implementation issues that directly affect the area, delay, and power dissipation of the MCM design. In this paper, we initially present area efficient addition and subtraction architectures used in the design of the MCM operation. Then, we propose an algorithm that searches an MCM design with the smallest area taking into account the cost of each operation at gate-level. To address the area and delay tradeoff in MCM design, the proposed algorithm is improved to find the smallest area solution under a delay constraint. The experimental results show that the proposed algorithms yield low-complexity and high-speed MCM designs with respect to those obtained by the prominent algorithms designed for the optimization of the number of operations and the optimization of area at gate-level.

Efficient Dedicated Multiplication Blocks for 2´s Complement Radix-2m Array Multipliers

Abstract: In this paper, we introduce new dedicated blocks for radix-2 m multiplication. These blocks are basic components of the structure of the 2´s complement radix-2 m array multiplier previously proposed in the literature. In the original array multiplier, the blocks that perform the radix-2 m multiplication were automatically synthesized from a truth table. The dedicated multiplication blocks we propose are themselves composed of a structure of less complex multiplication blocks and resort to efficient Carry Save adders (CSA). This new scheme can be naturally extended for different radices multiplication. We present results of area, delay and power consumption for 16, 32 and 64 bit array multipliers using the new dedicated modules. The results show that by using the new dedicated modules, the array multipliers are more efficient in terms of delay and power consumption when compared both against the original array structure and the Modified Booth multiplier.

A new quaternary FPGA based on a voltage-mode multi-valued circuit

Abstract: FPGA structures are widely used due to early time-to-market and reduced non-recurring engineering costs in comparison to ASIC designs. Interconnections play a crucial role in modern FPGAs, because they dominate delay, power and area. Multiple-valued logic allows the reduction of the number of signals in the circuit, hence can serve as a mean to effectively curtail the impact of interconnections. In this work we propose a new FPGA structure based on a low-power quaternary voltage-mode device. The most important characteristics of the proposed architecture are the reduced fanout, low number of wires and switches, and the small wire length. We use a set of FIR filters as a demonstrator of the benefits of the quaternary representation in FPGAs. Results show a significant reduction on power consumption with small timing penalties.

Integrated circuit and system design : power and timing modeling, optimization and simulation : 19th international workshop, PATMOS 2009, Delft, the Netherlands, September 9-11, 2009 : revised selected papers

Abstract: Keynotes.- Robust Low Power Embedded SRAM Design: From System to Memory Cell.- Variability in Advanced Nanometer Technologies: Challenges and Solutions.- Subthreshold Circuit Design for Ultra-Low-Power Applications.- Special Session.- SystemC AMS Extensions: New Language - New Methods - New Applications.- Session 1: Variability & Statistical Timing.- Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation.- Interpreting SSTA Results with Correlation.- Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units.- Exponent Monte Carlo for Quick Statistical Circuit Simulation.- Poster Session 1: Circuit Level Techniques.- Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis.- A Hardware Implementation of the User-Centric Display Energy Management.- On-chip Thermal Modeling Based on SPICE Simulation.- Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures.- Session 2: Power Management.- Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip.- Data-Driven Clock Gating for Digital Filters.- Power Management and Its Impact on Power Supply Noise.- Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systems.- Session 3: Low Power Circuits & Technology.- Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique.- Crosstalk in High-Performance Asynchronous Designs.- Modeling and Reducing EMI in GALS and Synchronous Systems.- Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop.- Poster Session 2: System Level Techniques.- Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms.- Dynamic Data Type Optimization and Memory Assignment Methodologies.- Accelerating Embedded Software Power Profiling Using Run-Time Power Emulation.- Write Invalidation Analysis in Chip Multiprocessors.- Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform.- BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation.- Session 4: Power & Timing Optimization Techniques.- Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering.- Low Energy Voltage Dithering in Dual V DD Circuits.- Product On-Chip Process Compensation for Low Power and Yield Enhancement.- Session 5: Self-timed Circuits.- Low-Power Soft Error Hardened Latch.- Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities.- Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical Implementation.- The Magic Rule of Tiles: Virtual Delay Insensitivity.- Session 6: Low Power Circuit Analysis & Optimization.- Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates.- A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).- Routing Resistance Influence in Loading Effect on Leakage Analysis.- Session 7: Low Power Design Studies.- Processor Customization for Software Implementation of the AES Algorithm for Wireless Sensor Networks.- An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process.- Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V t Domain By Architectural Folding.- A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder.

Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach

Abstract: This paper proposes the implementation of fully-parallel radix-2 Decimation in Time (DIT) Fast Fourier Transform - FFT, using the Matrix- Multiple Constant Multiplication (M-MCM) at gate level In the FFT algorithm, the butterfly plays a central role in the complex multiplications by constants The use of the Matrix-MCM approach can reduce significantly the impact of real and imaginary multiplications by constants In this work, for each stage of the real and imaginary parts of the butterflies, we maximize the sharing of the partial products of the coefficients using M-MCM The experimental results show that 58% and 74% reduction in area and power dissipation respectively can be obtained by using the M-MCM approach when the FFT designs are synthesized using the CADENCE Encounter RTL Compiler under the UMC 130nm technology

Optimally Solving the MCM Problem Using Pseudo-Boolean Satisfiability

Abstract: In this report, we describe three encodings of the multiple constant multiplication (MCM) problem to pseudo-boolean satisfiability (PBS), and introduce an algorithm to solve the MCM problem optimally. To the best of our knowledge, the proposed encodings and the optimization algorithm are the first formalization of the MCM problem in a PBS manner. This report evaluates the complexity of the problem size and the performance of several PBS solvers over three encodings.

Analysis of the conditions for worst case switching activity in integrated circuits

Abstract: Relentless advances in IC technologies have fueled steady increases on fabricated component density and work frequencies. As feature sizes decrease to nanometer scales, an increase in switching activity per unit of area and time is observed. When extreme switching activity occurs in a small region of an integrated circuit, malfunctions may be caused either as a consequence of a decrease in bias levels in the power grid caused by IR-drop, or due to unexpected gates output glitching caused by ground bounce. For proper circuit verification, both conditions have to be estimated and accounted for. In this paper we propose and compare methods for the identification of the conditions leading to extreme situations of switching activity in integrated circuits. Based on the results obtained we propose a method to determining the exact conditions for worst case switching activity in small areas of a circuit and in small intervals of time.

Voltage-mode quaternary FPGAs: An evaluation of interconnections

Abstract: This work presents a study about FPGA interconnections and evaluates their effects on voltage-mode binary and quaternary FPGA structures. FPGAs are widely used due to the fast time-to-market and reduced non-recurring engineering costs in comparison to ASIC designs. Interconnections play a crucial role in modern FPGAs, because they dominate delay, power and area. The use of multiple-valued logic allows the reduction of the number of signals in the circuit, hence providing a mean to effectively curtail the impact of interconnections. The most important characteristic of the results are the reduced fanout, fewer number of wires and the smaller wire length presented by the quaternary devices. We use a set of arithmetic circuits to compare binary and quaternary implementations. This work presents the first step on developing quaternary circuits by mapping any binary random logic onto quaternary devices.