Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components.

A survey of design techniques for system-level dynamic power management : Special section on low-power electronics and design

Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited) In this paper, we survey several approaches to system-level dynamic power management We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components

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A survey of design techniques for system-level dynamic power management

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW. >

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Minimizing power consumption in digital CMOS circuits

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review of the power estimation techniques that have recently been proposed. >

A survey of power estimation techniques in VLSI circuits

Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical, and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

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Power minimization in IC design: principles and applications

In the paper, we propose a new metric for the minimization of area in the generic problem of multiple constant multiplications, and demonstrate its effectiveness for digital FIR filters. Previous methods use the number of required additions or subtractions as a cost function. We make the observation that not all of these operations have the same design cost. In the proposed algorithm, a minimum area solution is obtained by considering area estimates for each operation. To this end, we introduce accurate hardware models for addition and subtraction operations in terms of gate-level metrics, under both signed and unsigned representations. Our algorithm not only computes the best design solution among those that have the same number of operations, but is also able to find better area solutions using a non-minimum number of operations. The results obtained by the proposed exact algorithm are compared with the results of the exact algorithm designed for the minimum number of operations on FIR filters and it is shown that the area of the design can be reduced by up to 18%.

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Optimization of area in digital FIR filters using gate-level metrics

Finite impulse response (FIR) filtering is a ubiquitous operation in digital signal processing systems and is generally implemented in full custom circuits due to high-speed and low-power design requirements. The complexity of an FIR filter is dominated by the multiplication of a large number of filter coefficients by the filter input or its time-shifted versions. Over the years, many high-level synthesis algorithms and filter architectures have been introduced in order to design FIR filters efficiently. This article reviews how constant multiplications can be designed using shifts and adders/subtractors that are maximally shared through a high-level synthesis algorithm based on some optimization criteria. It also presents different forms of FIR filters, namely, direct, transposed, and hybrid and shows how constant multiplications in each filter form can be realized under a shift-adds architecture. More importantly, it explores the impact of the multiplierless realization of each filter form on area, delay, and power dissipation of both custom (ASIC) and reconfigurable (FPGA) circuits by carrying out experiments with different bitwidths of filter input, design libraries, reconfigurable target devices, and optimization criteria in high-level synthesis algorithms.

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A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures

In the last two decades, many efficient algorithms and architectures have been introduced for the design of low-complexity bit-parallel multiple constant multiplications (MCM) operation which dominates the complexity of many digital signal processing systems. On the other hand, little attention has been given to the digit-serial MCM design that offers alternative low-complexity MCM operations albeit at the cost of an increased delay. In this paper, we address the problem of optimizing the gate-level area in digit-serial MCM designs and introduce high-level synthesis algorithms, design architectures, and a computer-aided design tool. Experimental results show the efficiency of the proposed optimization algorithms and of the digit-serial MCM architectures in the design of digit-serial MCM operations and finite impulse response filters.

Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool

1 Introduction.- 1.1 Power as a Design Constraint.- 1.2 Organization of this Book.- References.- 2 Power Estimation.- 2.1 Power Dissipation Model.- 2.2 Switching Activity Estimation.- 2.2.1 Simulation-Based Techniques.- 2.2.2 Issues in Probabilistic Estimation Techniques.- 2.2.3 Probabilistic Techniques.- 2.3 Summary.- References.- 3 A Power Estimation Method for Combinational Circuits.- 3.1 Symbolic Simulation.- 3.2 Transparent Latches.- 3.3 Modeling Inertial Delay.- 3.4 Power Estimation Results.- 3.5 Summary.- References.- 4 Power Estimation for Sequential Circuits.- 4.1 Pipelines.- 4.2 Finite State Machines: Exact Method.- 4.2.1 Modeling Temporal Correlation.- 4.2.2 State Probability Computation.- 4.2.3 Power Estimation given State Probabilities.- 4.3 Finite State Machines: Approximate Method.- 4.3.1 Basis for the Approximation.- 4.3.2 Computing Present State Line Probabilities.- 4.3.3 Picard-Peano Method.- 4.3.4 Newton-Raphson Method.- 4.3.5 Improving Accuracy using m-Expanded Networks.- 4.3.6 Improving Accuracy using k-Unrolled Networks.- 4.3.7 Redundant State Lines.- 4.4 Results on Sequential Power Estimation Techniques.- 4.5 Modeling Correlation of Input Sequences.- 4.5.1 Completely and Incompletely Specified Input Sequences.- 4.5.2 Assembly Programs.- 4.5.3 Experimental Results.- 4.6 Summary.- References.- 5 Optimization Techniques for Low Power Circuits.- 5.1 Power Optimization by Transistor Sizing.- 5.2 Combinational Logic Level Optimization.- 5.2.1 Path Balancing.- 5.2.2 Don't-care Optimization.- 5.2.3 Logic Factorization.- 5.2.4 Technology Mapping.- 5.3 Sequential Optimization.- 5.3.1 State Encoding.- 5.3.2 Encoding in the Datapath.- 5.3.3 Gated Clocks.- 5.4 Summary.- References.- 6 Retiming for Low Power.- 6.1 Review of Retiming.- 6.1.1 Basic Concepts.- 6.1.2 Applications of Retiming.- 6.2 Retiming for Low Power.- 6.2.1 Cost Function.- 6.2.2 Verifying a Given Clock Period.- 6.2.3 Retiming Constraints.- 6.2.4 Executing the Retiming.- 6.3 Experimental Results.- 6.4 Conclusions.- References.- 7 Precomputation.- 7.1 Subset Input Disabling Precomputation.- 7.1.1 Subset Input Disabling Precomputation Architecture.- 7.1.2 An Example.- 7.1.3 Synthesis of Precomputation Logic.- 7.1.4 Multiple-Output Functions.- 7.1.5 Examples of Precomputation Applied to Datapath Modules.- 7.1.6 Multiple Cycle Precomputation.- 7.1.7 Experimental Results for the Subset Input Disabling Architecture.- 7.2 Complete Input Disabling Precomputation.- 7.2.1 Complete Input Disabling Precomputation Architecture.- 7.2.2 An Example.- 7.2.3 Synthesis of Precomputation Logic.- 7.2.4 Simplifying the Original Combinational Logic Block.- 7.2.5 Multiple-Output Functions.- 7.2.6 Experimental Results for the Complete Input Disabling Architecture.- 7.3 Combinational Precomputation.- 7.3.1 Combinational Logic Precomputation.- 7.3.2 Precomputation at the Inputs.- 7.3.3 Precomputation for Arbitrary Sub-Circuits in a Circuit.- 7.3.4 Experimental Results for the Combinational Precomputation Architecture.- 7.4 Multiplexor-Based Precomputation.- 7.5 Conclusions.- References.- 8 High-Level Power Estimation and Optimization.- 8.1 Register Transfer Level Power Estimation.- 8.1.1 Functional Modules.- 8.1.2 Controller.- 8.1.3 Interconnect.- 8.2 Behavioral Level Synthesis for Low Power.- 8.2.1 Transformation Techniques.- 8.2.2 Scheduling Techniques.- 8.2.3 Allocation Techniques.- 8.2.4 Optimizations at the Register-Transfer Level.- 8.3 Conclusions.- References.- 9 Conclusion.- 9.1 Power Estimation at the Logic Level.- 9.2 Optimization Techniques at the Logic Level.- 9.3 Estimation and Optimization Techniques at the RT Level.- References.

Computer-Aided Design Techniques for Low Power Sequential Logic Circuits

We describe an approach to estimate the average power dissipation in sequential logic circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit power estimation are limited by the fact that the input sequences to the sequential circuit are assumed to be uncorrelated. In reality, the inputs come from other sequential circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power estimation can be carried out using existing sequential circuit power estimation methods on a cascade circuit consisting of the IMFSM and the original sequential circuit.

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José Monteiro

Papers

Optimization of area in digital FIR filters using gate-level metrics

A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures

Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool

Computer-Aided Design Techniques for Low Power Sequential Logic Circuits

Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs