J
José Monteiro
Researcher at Instituto Superior Técnico
Publications - 137
Citations - 2665
José Monteiro is an academic researcher from Instituto Superior Técnico. The author has contributed to research in topics: Sequential logic & Multiplication. The author has an hindex of 26, co-authored 135 publications receiving 2555 citations. Previous affiliations of José Monteiro include University of Lisbon & Technical University of Lisbon.
Papers
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Proceedings ArticleDOI
A new architecture for 2's complement Gray encoded array multiplier
TL;DR: A hybrid encoding is proposed for the architecture, which is a compromise between the minimal input dependency presented by binary encoding and the low switching characteristic of the Gray encoding, to reduce the switching activity both internally and at the inputs.
Proceedings ArticleDOI
Bitwise encoding of finite state machines
TL;DR: Experimental results indicate that the method of iteratively defining one bit at a time can generally achieve superior results to existing sequential state assignment methods which try to solve large problems heuristically.
Book ChapterDOI
Multiplierless Design of Linear DSP Transforms
TL;DR: This chapter addresses the problem of minimizing the number of addition and subtraction operations in a CMVM operation and introduces a hybrid algorithm that incorporates efficient techniques and describes how the hybrid algorithm can be modified to handle a delay constraint.
Book ChapterDOI
Generating Worst-Case Stimuli for Accurate Power Grid Analysis
TL;DR: This paper proposes a methodology for computation of the worst-case stimuli for power grid analysis by determining the input vector that maximizes the number of gates, in close proximity to each other, that can switch in a given time window.
Journal ArticleDOI
A novel method for the approximation of multiplierless constant matrix vector multiplication
TL;DR: An approximation algorithm, called aura, for the multiplierless design of the constant matrix vector multiplication (CMVM) which is a ubiquitous operation in DSP systems and can generate alternative CMVM designs under different error constraints, enabling a designer to choose the one that fits best in an application.