Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components.

A survey of design techniques for system-level dynamic power management : Special section on low-power electronics and design

Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited) In this paper, we survey several approaches to system-level dynamic power management We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components

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A survey of design techniques for system-level dynamic power management

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW. >

/pdf/minimizing-power-consumption-in-digital-cmos-circuits-2ibdk90up4.pdf

Minimizing power consumption in digital CMOS circuits

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review of the power estimation techniques that have recently been proposed. >

A survey of power estimation techniques in VLSI circuits

Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical, and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

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Power minimization in IC design: principles and applications

https://repositorio.chporto.pt/bitstream/10400.16/1093/1/DoencaDaInclusao_16-2_Webl.pdf

Doença da Inclusão das Microvilosidades: A importância do trabalho de enfermagem na doença crónica grave

In a recent work on multiple constant multiplication (MCM) problems, a fully predictable sub-linear runtime heuristic was introduced, called Radix-2 r MCM. This method shows competitive results in speed, power and area, comparatively with the leading algorithms. In this study, the authors combine Radix-2 r MCM with an exact common subexpression elimination (CSE) algorithm. The resulting algorithm denoted Radix-2 r -CSE allows a substantial reduction in the number of addition/subtraction operations in MCM by maximising the sharing of partial terms after an initial recoding in Radix-2 r MCM. The savings over Radix-2 r MCM ranges from 4.34 to 18.75% (10% on average) when considering a set of 14 benchmark finite impulse response filters of varying complexity.

Radix-2 r recoding with common subexpression elimination for multiple constant multiplication

This work presents a study about FPGA interconnections and evaluates their effects on voltage-mode binary and quaternary FPGA structures. FPGAs are widely used due to the fast time-to-market and reduced non-recurring engineering costs in comparison to ASIC designs. Interconnections play a crucial role in modern FPGAs, because they dominate delay, power and area. The use of multiple-valued logic allows the reduction of the number of signals in the circuit, hence providing a mean to effectively curtail the impact of interconnections. The most important characteristic of the results are the reduced fanout, fewer number of wires and the smaller wire length presented by the quaternary devices. We use a set of arithmetic circuits to compare binary and quaternary implementations. This work presents the first step on developing quaternary circuits by mapping any binary random logic onto quaternary devices.

/pdf/voltage-mode-quaternary-fpgas-an-evaluation-of-2xlj3j8m6t.pdf

Voltage-mode quaternary FPGAs: An evaluation of interconnections

Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significant power reductions are possible with techniques based on finite state machine (FSM) decomposition. A serious limitation of previously proposed techniques is that they require the state transition graph (STG) of the FSM to be given or extracted from the circuit. Since the size of the STG can be exponential on the number of registers in the circuit, explicit techniques can only be applied to relatively small sequential circuits. In this paper, we present a new approach to perform FSM decomposition by direct manipulation of the circuit. This way, we do not require the STG, either explicit or implicit, thus further avoiding the limitations imposed by the use of BDDs. Therefore, this technique can be applied to circuits with very large STGs. We provide a set of experimental results that show that power consumption can be substantially reduced, in some cases by more than 70%.

http://ieeexplore.ieee.org/iel5/6731/18001/00835123.pdf

FSM decomposition by direct circuit manipulation applied to low power design

The operation of retiming consists of repositioning the registers in a sequential circuit, while maintaining its external functional behavior. Retiming was first proposed in [3] as a technique to improve throughput by moving the registers in a circuit.

José Monteiro

Papers

Doença da Inclusão das Microvilosidades: A importância do trabalho de enfermagem na doença crónica grave

Radix-2 r recoding with common subexpression elimination for multiple constant multiplication

Voltage-mode quaternary FPGAs: An evaluation of interconnections

FSM decomposition by direct circuit manipulation applied to low power design

Retiming for Low Power