Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components.

A survey of design techniques for system-level dynamic power management : Special section on low-power electronics and design

Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited) In this paper, we survey several approaches to system-level dynamic power management We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components

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A survey of design techniques for system-level dynamic power management

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW. >

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Minimizing power consumption in digital CMOS circuits

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review of the power estimation techniques that have recently been proposed. >

A survey of power estimation techniques in VLSI circuits

Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical, and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

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Power minimization in IC design: principles and applications

The analysis of input conditions that may cause a short-circuit in a logic circuit has recently become a critical issue, due to the potential presence of parasitic circuit elements after layout. This analysis is strongly related to the problem of determining paths in a graph whose edges are defined by related logic functions. Logic circuits can be modeled as a generic graph, where edges are a logic function of static input variable combinations, representing transistors that act like logic switches. The solution to this problem must address a complex SAT-problem involving an extensive inspection of all possible paths between two nodes, the power supply and ground. We describe an efficient method, based on a Quantified Boolean Formula (QBF) model, that solves this problem in an incremental way. We propose a parallel implementation for multi-core shared-memory machines. The Espresso logic minimization tool was critical to keep the size of the intermediate logic functions manageable. In order to be able to use this tool in parallel, we developed a thread-safe version of Espresso and have made it available to the community. The proposed solution was validated against a set of benchmarks that show the effectiveness of our parallel implementation, allowing to address instances of transistor-level circuits for a wide range of inputs and internal nodes efficiently.

Short-circuit Analysis using a Parallel QBF Solver

Since human beings have limited perceptual abilities, in many digital signal processing (DSP) applications, e.g., image and video processing, the outputs do not need to be computed accurately. Instead, they can be approximated so that the area, delay, and/or power dissipation of the design can be reduced. This paper presents an approximation algorithm, called AURA, for the multiplierless design of the constant matrix vector multiplication (CMVM) which is a ubiquitous operation in DSP systems. AURA aims to tune the constants such that the resulting matrix leads to a CMVM design which requires the fewest adders/subtractors, satisfying the given error constraints. This paper also introduces its modified version, called AURA-DC, which can reduce the delay of the CMVM operation with a small increase in the number of adders/subtractors. Experimental results show that the proposed algorithms yield significant reductions in the number of adders/subtractors with respect to the original realizations without violating the error constraints, and consequently, lead to CMVM designs with less area, delay, and power dissipation. Moreover, they can generate alternative CMVM designs under different error constraints, enabling a designer to choose the one that fits best in an application.

A Novel Method for the Approximation of Multiplierless Constant Matrix Vector Multiplication

The methods of Chapter 7 are limited by the predefined logical structure of the circuit. Techniques at a higher abstraction levels, namely behavioral and register-transfer levels, yield a potentially larger optimization impact since these constraints do not yet exist. Further, logic level descriptions are too detailed to allow optimization methods to be applied to large designs.

High-Level Power Estimation and Optimization

The multiplication of a variable by a single constant selected from a set of fixed constants at a time, called the time-multiplexed constant multiplication (TMCM), is frequently used in digital signal processing (DSP) systems. Existing algorithms implement the TMCM operation using multiplexers (MUXes), adders/subtractors, and shifts, and reduce its complexity by merging single/multiple constant multiplication graphs and by sharing the basic structures. This paper introduces ARION, that exploits the most common partial terms in the TMCM design on top of the previously proposed DAGfusion algorithm, which merges the single constant multiplication graphs. Experimental results show that ARION obtains significantly better solutions than prominent TMCM methods.

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Towards the least complex time-multiplexed constant multiplication

Relentless advances in IC technologies have fueled steady increases on fabricated component density and working frequencies. As feature sizes decrease to nanometer scales, an increase in switching activity per unit of area and time is observed. When extreme switching activity occurs in a small region of an integrated circuit, malfunctions may be triggered that compromise behavior. This can be either a consequence of a decrease in bias levels in the power grid caused by IR-Drop, or due to unexpected glitching on gates' outputs caused by ground bounce. For proper circuit verification, both conditions have to be accurately estimated and accounted for. Achieving this in an accurate manner for a large circuit is a very challenging problem. In this paper we propose and compare methods for the identification of the conditions leading to extreme situations of switching activity in integrated circuits. Our approach is based on both spatial and time partitioning which are used to address the accuracy and computational requirements. We propose a method for determining the exact conditions for worst case switching activity in a small circuit area during a short time interval. We then show how this method can be combined with partitioning to allow for accurate full circuit verification.

José Monteiro

Papers

Short-circuit Analysis using a Parallel QBF Solver

A Novel Method for the Approximation of Multiplierless Constant Matrix Vector Multiplication

High-Level Power Estimation and Optimization

Towards the least complex time-multiplexed constant multiplication

Analysis of the conditions for the worst case switching activity in integrated circuits