J
José Monteiro
Researcher at Instituto Superior Técnico
Publications - 137
Citations - 2665
José Monteiro is an academic researcher from Instituto Superior Técnico. The author has contributed to research in topics: Sequential logic & Multiplication. The author has an hindex of 26, co-authored 135 publications receiving 2555 citations. Previous affiliations of José Monteiro include University of Lisbon & Technical University of Lisbon.
Papers
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Journal ArticleDOI
Automatic equivalence checking of programs with uninterpreted functions and integer arithmetic
Nuno P. Lopes,José Monteiro +1 more
TL;DR: This paper proposes the first semi-algorithm for the automatic verification of partial equivalence of two programs over the combined theory of uninterpreted function symbols and integer arithmetic (UF+IA), and shows that it can prove more optimizations correct than state-of-the-art techniques.
Proceedings ArticleDOI
Optimization of combinational and sequential logic circuits for low power using precomputation
TL;DR: New precomputation architectures for both combinational and sequential logic and new precomPUTation-based logic synthesis methods that optimize logic circuits for low power are presented.
Journal ArticleDOI
Rett syndrome with and without detected MECP2 mutations: An attempt to redefine phenotypes
Teresa Temudo,Mónica Santos,Mónica Santos,Elisabete Ramos,Karin Dias,José Pedro Vieira,Ana S. P. Moreira,Eulália Calado,Inês Carrilho,Guiomar Oliveira,Antonio Levy,Clara Barbot,Maria João Fonseca,Alexandra Cabral,Pedro Cabral,José Monteiro,Luís Borges,R. Gomes,Graça Mira,Susana Aires Pereira,Manuela M. Santos,Anabela Fernandes,Jörg T. Epplen,Jorge Sequeiros,Jorge Sequeiros,Patrícia Maciel +25 more
TL;DR: A clear regressive period and the presence of more than three different stereotypies, rigidity and ataxic-rigid gait seemed to be very helpful in differentiating Group I from Group II.
Journal ArticleDOI
Implicit FSM decomposition applied to low-power design
TL;DR: This paper describes a clock-gating technique based on the computation of two sub-FSMs that together have the same functionality as the original FSM, and proposes a method that implicitly performs the FSM decomposition.
Journal ArticleDOI
Sequential logic optimization for low power using input-disabling precomputation architectures
TL;DR: A method to automatically synthesize precomputation logic for this architecture is presented, and it is shown that it is significantly more powerful than the architecture previously treated in the literature.