Showing papers by "Jose Silva-Martinez published in 1990"
TL;DR: In this paper, a very linear CMOS floating resistor is introduced to take advantage of the MOS transistor characteristics biased in the linear region, which can be improved by reducing the AC voltage swing in the transistor terminals, the drain and the source, and using the linear behaviour between the gate voltage and the drain current.
Abstract: A very linear CMOS floating resistor is introduced. The proposed topology takes advantage of the MOS transistor characteristics biased in the linear region. It is claimed that the resistor linearity can be improved by reducing the AC voltage swing in the transistor terminals, the drain and the source, and using the linear behaviour between the gate voltage and the drain current. Simulated results, even in the presence of large transistors mismatches, have shown that the total harmonic distortion (THD) is lower than 0.1% for applied voltages up to 2 V peak to peak, VPTP. Resistance values of 500Ω and a frequency response up to 10MHz have been simulated in a typical 3 =m CMOS process. The supply voltages was only ± 2.5 V.
23 citations
TL;DR: In this article, a switch-capacitor (SC) equalizer with three operational amplifiers and six capacitor banks is presented, which can independently control the center frequency, bandwidth and peak voltage gain steps for the bump (and dip) frequency response.
Abstract: A versatile and economical switched-capacitor (SC) equalizing structure to compensate attenuation characteristics is presented. The monolithic SC bump equalizer has three operational amplifiers and six capacitor banks to independently control the center frequency, bandwidth, and peak voltage gain steps for the bump (and dip) frequency response. The bump equalizer has been integrated using 3- mu m CMOS (p-well) technology and occupies an area of 3.36 mm/sup 2/, including an additional test amplifier and test buffer. The circuit operating from +or-5-V power supplies typically dissipates 60 mW when sampled at 75 kHz. >
21 citations
Proceedings Article•
01 Jan 1990TL;DR: In this paper, a high frequency very low distortion transconductor is introduced, which is used in a second order filter for a transconductance amplifier with a 3?m N-well process.
Abstract: A high frequency very low distortion transconductor is introduced. The Total Harmonic Distortion (THD) is lower than -60 dB's for a differential input voltage of 2.4 Vptp (Volts peak to peak), which represents 41 % ofthe transconductor bias current. The dynamic range is in the order of 84 dB's. Furthermore, this structure presents low sensitivity to mismatches. The supply voltages are only +/- 2.5 volts. An Operational Transconductance Amplifier (OTA) and a second order filter, based in the proposed transconductor, have been fabricated in a 3 ?m N-well process. The OTA transconductance is 150?A/V and the center frequency of the filter is 1.75 MHz. The quality factor can be adjusted from 1 to 50. The experimental results are in good agreement with the expected and simulated results.
5 citations