Showing papers by "Jose Silva-Martinez published in 2016"

A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration

Abstract: Evolutionary computation, learning theory, neural networks, and fuzzy logic, are just few of the disciplines known as computational intelligence. In today's science and technology, computational intelligence techniques are widely used. They make use of computers' storage-and-speed abilities to address complex mathematical problems, which are difficult to be solved by conventional mathematical reasoning. In this paper, we introduce the design of a complex digital system implementing an evolutionary-computation algorithm to calibrate the mismatches affecting the performance of a time-interleaved Analog-to-Digital converter (TIADC). An error function (EF) is devised by modeling the three main issues limiting time-interleaved ADC performance: gain mismatches, offset mismatches and timing skews. The digital system is implemented on a Field-Programmable-Gate-Array (FPGA) and its digital logic and functionalities are tested by matching its simulation results against a Verilog-A behavioral model of the complete TIADC.

A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS

Abstract: This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA drivers and segments are switched on and off according to signal power; thus, the PA power consumption correlates with the power of the input signal. Binary power gain variations due to PA segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the tradeoffs between power efficiency and linearity by employing the digital predistortion technique. The PA is implemented in a 40 nm CMOS process. It delivers a saturated output power of 35 dBm with 44.9% peak power-added efficiency (PAE) and a linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at $\pm {5}\;\text{MHz}$ at a maximum linear output power of 31 dBm for a baseband WCDMA signal is $- {35}.{8}\;\text{dBc}$ .

A 4 Bit Continuous-Time $\Sigma \Delta $ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer

Abstract: This paper presents a fully digital quantization noise reduction algorithm (DQNRA) for $\mathrm {CT}\Sigma \Delta \mathrm {M}$ . The algorithm overcomes the signal leakage issues commonly found in cascade and MASH implementations. The proposed DQNRA is robust to PVT variations. The DQNRA performs a foreground measurement of the modulators noise transfer function. A $\Sigma \Delta \mathrm {M}$ using a 7 bit quantizer, from which the four most significant bits are used for the operation of the $\Sigma \Delta \mathrm {M}$ , proves the DQNRA concept. The remaining three least significant bits are used for the realization of the DQNRA for quantization noise improvement. A 7 bit quantizer with a three-step subranging architecture is implemented to reduce power and area consumption. A fourth-order continuous-time $\Sigma \Delta $ prototype was implemented in 130 nm CMOS technology. The modulator’s total power consumption is 20 mW, with only 6 mW used for the realization of the 7 bit quantizer operating at 500 MHz. For this prototype, the use of a DQNRA algorithm improved the modulator’s SNDR from 69 to 75 dB over a 15 MHz bandwidth, limited after calibration by thermal noise rather than quantization noise. The obtained FoM is 164 dB.

Low noise amplifier

Abstract: An amplifier for signal amplification, the amplifier comprising: a signal input arrangement; a signal output arrangement; a first transistor (Q 1 ); a second transistor (Q 2 ); and a third transistor (Q 3 ), wherein: the first (Q 1 ), second (Q 2 ) and third (Q 3 ) transistors are coupled to one another to form a transconductance cell, the transconductance cell is coupled to the signal input arrangement and the signal output arrangement, and the transconductance cell is operable to receive a first signal from the signal input arrangement, amplify the first signal and output an amplified first signal to the signal output arrangement. There is also disclosed a receiver incorporating the amplifier and methods of operating the amplifier.

Design of minimally invasive all-pole analog lowpass filters

Abstract: In this paper, a new design technique for designing higher order minimally invasive lowpass filters is proposed. The proposed fully differential filter has been simulated in TSMC 130 nm technology for third and fourth orders. When compared with the conventional filter implementations such as a Tow-Thomas architecture, the proposed third order solution achieves a total in-band input-referred integrated noise of $$44.09\,\upmu V$$44.09μV compared to $$78.83\,\upmu V$$78.83μV, achieved by a Tow-Thomas implementation. The proposed solution offers higher tolerance to blockers along with lesser number of active devices required. Though, the total capacitance used is increased from 23.82 pF to 89.82 pF, from third order Tow-Thomas filter to its minimally invasive filter counterpart, the power consumption reduces by $$77\,\%$$77% from third order Tow-Thomas to the third order minimally invasive filter.