The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

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High-K materials and metal gates for CMOS applications

Germanium CMOS potential from material and process perspectives: Be more positive about germanium

Addition of MgO nanoparticles and plasma surface treatment of three-dimensional printed polycaprolactone/hydroxyapatite scaffolds for improving bone regeneration.

The aim of this review paper is to describe the impact of so-called border traps (BTs) in high- k gate oxides on the operation and reliability of high-mobility channel transistors. First, a brief summary of the physics of BTs will be given, describing the charge trapping and release in terms of the elastic tunneling model. It will be also pointed out how information on the BT properties can be extracted from popular measurement techniques such as low-frequency (1/f) noise and variable-frequency charge pumping. In the next two parts, the impact of BTs on metal-oxide-semiconductor structures fabricated on Ge or III-V channel materials is outlined, with particular emphasis on the development of novel or adapted measurement techniques such as AC transconductance dispersion or trap spectroscopy by charge injection and sensing. Finally, the effect of BTs on the operation and reliability of high-mobility channel MOSFETs is discussed. It is also shown that the density of BTs is closely linked to the quality or defectivity of the high- k gate stack, indicating room for improvement by optimization of processing or by implementation of a suitable bulk-oxide defect passivation step.

Border Traps in Ge/III–V Channel Devices: Analysis and Reliability Aspects

We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at VDS=-0.5 V, good short-channel effect control, and high transconductance (gm=1.2 mS/μm at VDS=-1 V and 1.05 mS/μm at VDS=-0.5 V for LG=70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.

Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping

An ultrathin equivalent oxide thickness (EOT) HfO2/Al2O3/Ge gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al2O3 layer between HfO2 and Ge for suppressing HfO2-GeOx intermixing, resulting in a low-interface-state-density (Dit) GeOx/Ge metal-oxide-semiconductor (MOS) interface. The EOT of these gate stacks has been scaled down to 0.7-0.8 nm with maintaining the Dit in 1011 cm-2·eV-1 level. The p- and n-channel MOS field-effect transistors (MOSFETs) (p- and n-MOSFETs) using this gate stack have been fabricated on (100) Ge substrates and exhibit high hole and electron mobilities. It is found that the Ge p- and n-MOSFETs exhibit peak hole mobilities of 596 and 546 cm2/V·s and peak electron mobilities of 754 and 689 cm2/V·s at EOTs of 0.82 and 0.76 nm, respectively, which are the record-high reports so far for Ge MOSFETs in subnanometer EOT range because of the sufficiently passivated Ge MOS interfaces in present HfO2/Al2O3/GeOx/Ge gate stacks.

High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using $\hbox{HfO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}$ Gate Stacks Fabricated by Plasma Postoxidation

GeOx/Ge interfaces are fabricated by plasma post oxidation of Al2O3/Ge (100) structures at 300 °C and room temperature (RT). It is found that reduction of oxidation temperature results in a significant decrease of the GeOx/Ge interface roughness and a slight increase of the interface trap density. The Ge p- and n-channel MOSFETs with the GeOx/Ge interfaces oxidized at the RT provide 20% and 25% enhancement, respectively, of high field hole and electron mobilities than those of MOSFETs oxidized at 300 °C. This mobility enhancement is attributable to the reduction of GeOx/Ge interface roughness, which has been proven by theoretical calculation of surface-roughness-limited mobility using the real MOS interface roughness directly extracted from transmission electron microscopy results. As a result, high hole and electron mobility of 179 and 378 cm2/Vs, respectively, have been obtained at a Ns of 1013 cm-2 in MOSFETs fabricated by the RT plasma post oxidation.

Impact of Plasma Postoxidation Temperature on the Electrical Properties of ${\rm Al}_{2}{\rm O}_{3}/{\rm GeO}_{x}/{\rm Ge}$ pMOSFETs and nMOSFETs

The ultrathin GeOx/Ge interfaces formed on Ge (100) and (111) surfaces by applying plasma post oxidation to thin Al2O3/Ge structures are characterized in detail using X-ray photoelectron spectroscopy (XPS) and transmission electron microscopy. It is found that the XPS signals assigned to Ge 1+ and the 2+ states in the GeOx layers by post plasma oxidation have oscillating behaviors on Ge (100) surfaces in a period of ∼0.3 nm with an increase in the GeOx thickness. Additionally, the oscillations of the signals assigned to Ge 1+ and 2+ states show opposite phase to each other. The similar oscillation behaviors are also confirmed on Ge (111) surfaces for Ge 1+ and 3+ states in a period of ∼0.5 nm. These phenomena can be strongly regarded as an evidence of the atomic layer-by-layer oxidation of GeOx/Ge interfaces on Ge (100) and (111) surfaces.

Atomic layer-by-layer oxidation of Ge (100) and (111) surfaces by plasma post oxidation of Al2O3/Ge structures

Hall measurements have been carried out for the Ge p-and n-MOSFETs with different substrate orientations and GeO x /Ge interface qualities. It is found that the significant reduction of effective mobility in high surface carrier concentration (N s ) or high normal field in Ge MOSFETs is attributed partly to the N s loss due to large amounts of interface states inside the valence and conduction bands of Ge. The GeO x /Ge interface roughness is another reason limiting the high N s mobility. It has been revealed that room temperature plasma post oxidation can realize Al 2 O 3 /GeO x /Ge gate stacks with atomically-flat GeO x /Ge interfaces. Ge MOSFETs with these interfaces have provided record high effective hole and electron mobility, which overcome the Si universal mobility in both low and high N s regions.

http://ieeexplore.ieee.org/iel7/6471855/6478950/06479051.pdf

Ju-Chin Lin

Papers

High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using $\hbox{HfO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}$ Gate Stacks Fabricated by Plasma Postoxidation

Impact of Plasma Postoxidation Temperature on the Electrical Properties of ${\rm Al}_{2}{\rm O}_{3}/{\rm GeO}_{x}/{\rm Ge}$ pMOSFETs and nMOSFETs

Atomic layer-by-layer oxidation of Ge (100) and (111) surfaces by plasma post oxidation of Al2O3/Ge structures

Physical mechanism determining Ge p- and n-MOSFETs mobility in high N s region and mobility improvement by atomically flat GeO x /Ge interfaces

Evidence of Layer-by-Layer Oxidation of Ge Surfaces by Plasma Oxidation Through Al2O3