https://iopscience.iop.org/article/10.7567/JJAP.57.06JA01/pdf

Progress in nanoscale dry processes for fabrication of high-aspect-ratio features: How can we control critical dimension uniformity at the bottom?

Fabrication of semiconductor devices having three-dimensional (3D) structures places unprecedented demands on plasma etching processes. Among these demands is the frequent need to simultaneously etch features with a wide variety of aspect ratios (AR) on the same wafer. Many plasma etching processes exhibit aspect ratio dependent etching (ARDE)—different etch rates for features that have different aspect ratios, usually slower for larger AR. Processes subject to ARDE require over-etch to clear the larger AR features, which increases the need for high selectivity and low damage. Despite these issues, the physical processes which contribute to ARDE are not well understood. In this paper, results are discussed from a computational investigation on the root causes of ARDE during Ar/Cl2 plasma etching of Si, and, in particular, the role which neutral transport plays in this process. Parametric studies were performed varying neutral-to-ion flux ratios, surface recombination rates of atomic Cl, and neutral and io...

Role of neutral transport in aspect ratio dependent plasma etching of three-dimensional features

Current (and future) microelectronics fabrication requirements place unprecedented demands on the fidelity of plasma etching. As device features shrink to atomic dimensions, the plasma etching processes used to define these devices must resolve these scales. By separating etching processes into cycles of multiple, self-limited steps, different physics processes which are closely coupled in traditional plasma etching can be largely decoupled and separately optimized. This technique, atomic layer etching (ALE), can ideally remove uniform layers of material with consistent thickness in each cycle. ALE holds the promise of improving uniformity, reducing damage, increasing selectivity, and minimizing aspect ratio dependent etching (ARDE) rates. The practical implementation of ALE depends on how close to ideal the system can be operated and the tolerance to nonideal conditions. In this paper, results are discussed from a computational investigation of the consequences of nonidealities in the ALE of silicon usin...

Atomic layer etching of 3D structures in silicon: Self-limiting and nonideal reactions

The ability to manufacture a nanogap in between two electrodes has proven a powerful catalyst for scientific discoveries in nanoscience and molecular electronics A wide range of bottom-up and top-down methodologies are now available to fabricate nanogaps that are less than 10 nm wide However, most available techniques involve time-consuming serial processes that are not compatible with large-scale manufacturing of nanogap devices The scalable manufacturing of sub-10 nm gaps remains a great technological challenge that currently hinders both experimental nanoscience and the prospects for commercial exploitation of nanogap devices Here, available nanogap fabrication methodologies are reviewed and a detailed comparison of their merits is provided, with special focus on large-scale and reproducible manufacturing of nanogaps The most promising approaches that could achieve a breakthrough in research and commercial applications are identified Emerging scalable nanogap manufacturing methodologies will ultimately enable applications with high scientific and societal impact, including high-speed whole genome sequencing, electromechanical computing, and molecular electronics using nanogap electrodes

Scalable Manufacturing of Nanogaps

Semiconductor device dimensions have been decreasing steadily over the past several decades, generating the need to overcome fundamental limitations of both the materials they are made of and the fabrication techniques used to build them. Modern metal gates are no longer a simple polysilicon layer, but rather consist of a stack of several different materials, often requiring multiple processing steps each, to obtain the characteristics needed for stable operation. In order to better understand the underlying mechanics and predict the potential of new methods and materials, technology computer aided design has become increasingly important. This review will discuss the fundamental methods, used to describe expected topology changes, and their respective benefits and limitations. In particular, common techniques used for effective modeling of the transport of molecular entities using numerical particle ray tracing in the feature scale region will be reviewed, taking into account the limitations they impose on chemical modeling. The modeling of surface chemistries and recent advances therein, which have enabled the identification of dominant etch mechanisms and the development of sophisticated chemical models, is further presented. Finally, recent advances in the modeling of gate stack pattering using advanced geometries in the feature scale are discussed, taking note of the underlying methods and their limitations, which still need to be overcome and are actively investigated.

https://www.mdpi.com/2072-666X/9/12/631/pdf

Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review.

Pattern transfer in microelectronics fabrication using plasma-assisted etching processes is being challenged by the three-dimensional (3d) structures of devices such as fin field effect transistors. Etching of 3d structures typically requires a longer over-etch time to clear material in corners, introducing additional selectivity challenges to maintain feature scale critical dimensions. Feature open area, orientation, aspect ratio, and proximity to other nearby structures can influence the outcome of the etch process. In this paper, the authors report on the development and application of a 3d profile simulator, the Monte Carlo feature profile model in the investigation of aspect ratio, and feature orientation dependent etching. In these studies, energy and angularly resolved reactant fluxes were provided by the hybrid plasma equipment model. Results from the model were validated with trends from experimental data. Using reactant fluxes from He/Cl2 and Ar/Cl2 inductively coupled plasmas, etching of two di...

Investigation of feature orientation and consequences of ion tilting during plasma etching with a three-dimensional feature profile simulator

In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML’s Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

Improving scanner wafer alignment performance by target optimization

In the Global 450mm Equipment Development Consortium (G450C), a 193i guided directed self-assembly (DSA) pattern has been used to create structures at the 14nm node and below. The first guided DSA patterned wafer was ready for etch process development within a month of the G450C’s first 193i patterned wafer availability with one litho pass. Etch processes were scaled up from 300mm to 450mm for a 28nm pitch STI stack and a 40nm pitch M1 BEOL stack. The effects of various process parameters were investigated to fine tune each process. Overall process window has been checked and compared. Excellent process stability results were shown for current etch chambers.

450mm etch process development and process chamber evaluation using 193i DSA guided pattern

During reactive ion plasma etching (RIE) of semiconductor materials, a strong correlation between etch rate and feature size, or more specifically feature aspect ratio (AR), is often observed. There have been several analytical models proposed to explain this aspect ratio dependent etch-rate (ARDE), also known as “RIE lag.”[1,2] While most analytical models only address individual causes of ARDE, the complexity of most etching reactions implies that several ARDE mechanisms may be at play. This complexity motivates the use of numerical models which are sensitive to all of the probable causes of ARDE to determine the dominant factor in any given etching reaction.

Jun Belen

Papers

Investigation of feature orientation and consequences of ion tilting during plasma etching with a three-dimensional feature profile simulator

Improving scanner wafer alignment performance by target optimization

450mm etch process development and process chamber evaluation using 193i DSA guided pattern

Origins of aspect ratio dependent etching in plasma materials processing