Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

This tutorial clarifies the axiomatic definition of (v(α); i(β)) circuit elements via a lookup table dubbed an A-pad, of admissible (v; i) signals measured via Gedanken probing circuits. The (v(α); i(β)) elements are ordered via a complexity metric. Under this metric, the memristor emerges naturally as the fourth element, characterized by a state-dependent Ohm's law. A logical generalization to memristive devices reveals a common fingerprint consisting of a dense continuum of pinched hysteresis loops whose area decreases with the frequency ω and tends to a straight line as ω ~ ∞, for all bipolar periodic signals and for all initial conditions. This common fingerprint suggests that the term memristor be used hence-forth as a moniker for memristive devices.

The Fourth Element.

m';tNO; Thisworkpresents detailed characterization andmodeling of 104 - experimentaldata thereset operation inresistive-switching memories basedon _ Powder file metaloxides. Ourexperimental results confirm previous ob- ' 10 servations that reset iscontrolled byJoule heating, providing an 102~~~~~~~~~~~~~~~~~~~~~~i

Conductive-filament switching analysis andself-accelerated thermal dissolution modelforreset inNiO-based RRAM

In this letter, we extensively investigate the nonlinear resistive switching characteristics of Si3N4-based resistive random access memory (RRAM) devices that contain an Al2O3 tunnel barrier layer to alleviate sneak path currents in the cross-point array structure. When the compliance current (ICC) exceeds 1 mA, the Ni/Si3N4/TiN device shows both unipolar and bipolar switching with Ohmic characteristics in the low resistance state. Nonlinear resistive switching characteristics were observed for this device when ICC was ≤100 μA. We fabricated Si3N4/Al2O3 bilayer devices with different tunnel barrier layer thickness and characterized their nonlinear characteristics and failure resistance during the reset process. Furthermore, we obtained stable multiple resistance levels in the devices by varying ICC and the stop voltage for the set and reset switching, respectively. Our results suggest that an Al2O3 tunnel barrier layer embedded in Si3N4-based RRAM devices offers considerable potential to realize high-dens...

Nonlinear and multilevel resistive switching memory in Ni/Si3N4/Al2O3/TiN structures

In this work, we propose a physical memristor/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship. The proposed model is capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time. The developed compact model has been validated against two physical devices, fitting unipolar and bipolar switching. With no requirement of Verilog-A code, LTSpice, and Spectre simulations reproduce distinctive phenomena such as the preforming state, voltage/cycle dependent random telegraph noise and device degradation.

/pdf/spice-compact-modeling-of-bipolar-unipolar-memristor-1j1qo2z5ak.pdf

SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds

High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges.We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling.We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful”requirements for the various enabling dielectric hard mask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements.We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.© 2019 The Electrochemical Society.

https://iopscience.iop.org/article/10.1149/2.0161910jss/pdf

Review—Beyond the highs and lows: A perspective on the future of dielectrics research for nanoelectronic devices

Cu/a-SiC/Au resistive memory cells are measured using voltage pulses and exhibit the highest ROFF/RON ratio recorded for any resistive memory. The switching kinetics are investigated and fitted to a numerical model, using thermal conductivity and resistivity properties of the dielectric. The SET mechanism of the Cu/a-SiC/Au memory cells is found to be due to ionic motion without joule heating contributions, whereas the RESET mechanism is found to be due to thermally assisted ionic motion. The conductive filament diameter is extracted to be around 4nm. The high thermal conductivity and resistivity for the Cu/a-SiC/Au memory cells result in slow switching but with high thermal reliability and stability, showing potential for use in harsh environments. Radiation properties of SiC memory cells are investigated. No change was seen in DC sweep or pulsed switching nor in conductive mechanisms, up to 2Mrad(Si) using 60Co gamma irradiation.

https://eprints.soton.ac.uk/379796/1/AIP_SiC_Switching_kinetics.pdf

Switching kinetics of SiC resistive memory for harsh environments

Resistive switching of W/amorphous (a)-SiOxCy:H/Cu resistive memories incorporating solely native back-end-of-line (BEOL) materials were studied A-SiC11:H, a-SiO09C07:H, and a-SiO15C02:H were exploited as switching layers for resistive memories which all show resistive-switching characteristics with ultrahigh ON/OFF ratios in the range of 106 to 1010 Ohmic conduction in the low resistance state is attributed to the formation of Cu conductive filament inside the a-SiOxCy:H switching layer Rupture of the conductive filament leads to current conduction dominated by Schottky emission through a-SiOxCy:H Schottky contacts Comparison of the switching characteristics suggests composition of the a-SiOxCy:H has influences on VFORM and VSET, and current conduction mechanisms These results demonstrate the capability to achieve functional W/a-SiOxCy:H/Cu using entirely BEOL native materials for future embedded resistive memoriesResistive switching of W/amorphous (a)-SiOxCy:H/Cu resistive memories incorporating solely native back-end-of-line (BEOL) materials were studied A-SiC11:H, a-SiO09C07:H, and a-SiO15C02:H were exploited as switching layers for resistive memories which all show resistive-switching characteristics with ultrahigh ON/OFF ratios in the range of 106 to 1010 Ohmic conduction in the low resistance state is attributed to the formation of Cu conductive filament inside the a-SiOxCy:H switching layer Rupture of the conductive filament leads to current conduction dominated by Schottky emission through a-SiOxCy:H Schottky contacts Comparison of the switching characteristics suggests composition of the a-SiOxCy:H has influences on VFORM and VSET, and current conduction mechanisms These results demonstrate the capability to achieve functional W/a-SiOxCy:H/Cu using entirely BEOL native materials for future embedded resistive memories

Back-end-of-line a-SiOxCy:H dielectrics for resistive memory

Cu/amorphous-SiC (a-SiC) electrochemical metallization memory cells have been fabricated with two different counter electrode (CE) materials, W and Au, in order to investigate the role of CEs in a non-oxide semiconductor switching matrix. In positive bipolar regime with Cu filaments forming and rupturing, the CE influences the OFF state resistance and minimum current compliance. Nevertheless, a similarity in SET kinetics is seen for both CEs, which differs from previously published SiO2 memories, confirming that CE effects are dependent on the switching layer material or type. Both a-SiC memories are able to switch in the negative bipolar regime, indicating Au and W filaments. This confirms that CEs can play an active role in a non-oxide semiconducting switching matrix, such as a-SiC. By comparing both Au and W CEs, this work shows that W is superior in terms of a higher ROFF/RON ratio, along with the ability to switch at lower current compliances making it a favourable material for future low energy applications. With its CMOS compatibility, a-SiC/W is an excellent choice for future resistive memory applications.

/pdf/active-counter-electrode-in-a-sic-electrochemical-5blhnczh3h.pdf

Junqing Fan

Papers

Review—Beyond the highs and lows: A perspective on the future of dielectrics research for nanoelectronic devices

Switching kinetics of SiC resistive memory for harsh environments

Back-end-of-line a-SiOxCy:H dielectrics for resistive memory

Active counter electrode in a-SiC electrochemical metallization memory

Microstructure and electrical properties of co-sputtered Cu embedded amorphous SiC