Numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors. When two-dimensional (2-D) electrostatic effects are small (and when the insulator capacitance is much less than the semiconductor (quantum) capacitance), the model reduces to Natori's theory of the ballistic MOSFET. The model also treats 2-D electrostatics and the quantum capacitance limit where the semiconductor quantum capacitance is much less than the insulator capacitance. This new model provides insights into the performance of MOSFETs near the scaling limit and a unified framework for assessing and comparing a variety of novel transistors.

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Theory of ballistic nanotransistors

The device physics of nanoscale MOSFETs is explored by numerical simulations of a model transistor. The physics of charge control, source velocity saturation due to thermal injection, and scattering in ultrasmall devices are examined. The results show that the essential physics of nanoscale MOSFETs can be understood in terms of a conceptually simple scattering model.

Essential physics of carrier transport in nanoscale MOSFETs

Quantization in the inversion layer and phase coherent transport are anticipated to have significant impact on device performance in “ballistic” nanoscale transistors. While the role of some quantum effects have been analyzed qualitatively using simple one-dimensional ballistic models, two-dimensional (2D) quantum mechanical simulation is important for quantitative results. In this paper, we present a framework for 2D quantum mechanical simulation of a nanotransistor/metal oxide field effect transistor. This framework consists of the nonequilibrium Green’s function equations solved self-consistently with Poisson’s equation. Solution of this set of equations is computationally intensive. An efficient algorithm to calculate the quantum mechanical 2D electron density has been developed. The method presented is comprehensive in that treatment includes the three open boundary conditions, where the narrow channel region opens into physically broad source, drain and gate regions. Results are presented for (i) dr...

Two-dimensional quantum mechanical modeling of nanotransistors

Ballistic effects in short channel high electron mobility transistors (HEMTs) greatly reduce the field effect mobility compared to that in long gate structures. This reduction is related to a finite electron acceleration time in the channel under the device gate. As an example, the field effect mobility at room temperature in 0.15-/spl mu/m gate AlGaAs/GaAs HEMTs cannot exceed 3000 cm/sup 2//V-s. These predictions are consistent with the values of the field effect mobility extracted from the measured AlGaAs/GaAs HEMT current-voltage characteristics.

Low ballistic mobility in submicron HEMTs

Within just a decade from the pioneering work demonstrating the utility of nanopores for molecular sensing, nanopores have emerged as versatile systems for single-molecule manipulation and analysis. In a typical setup, a gradient of the electrostatic potential captures charged solutes from the solution and forces them to move through a single nanopore, across an otherwise impermeable membrane. The ionic current blockades resulting from the presence of a solute in a nanopore can reveal the type of the solute, for example, the nucleotide makeup of a DNA strand. Despite great success, the microscopic mechanisms underlying the functionality of such stochastic sensors remain largely unknown, as it is not currently possible to characterize the microscopic conformations of single biomolecules directly in a nanopore and thereby unequivocally establish the causal relationship between the observables and the microscopic events. Such a relationship can be determined using molecular dynamics-a computational method that can accurately predict the time evolution of a molecular system starting from a given microscopic state. This article describes recent applications of this method to the process of DNA transport through biological and synthetic nanopores.

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Deciphering ionic current signatures of DNA transport through a nanopore.

We have achieved extremely high drive current performance and ballistic (T>0.8) transport using ultra-thin (<2 nm) gate oxides in sub-30 nm effective channel length nMOSFETs. The peak drive performance in an nMOSFET was observed at t/sub ox//spl ap/1.3 nm for a 1.5 V power supply voltage with T/sub n//spl ap/0.7, while the peak performance in a pMOSFET was observed at t/sub ox//spl ap/1.5 nm for a -1.5 V supply with T/sub p//spl ap/0.5. Since the carrier scattering in the channel is due predominately to interface roughness, reducing the transverse surface field, either by reducing the gate voltage or by increasing the oxide thickness, can be used to improve the transmittance T/sub n//spl rarr/0.85, T/sub p//spl rarr/0.6, while diminishing the drive current.

The ballistic nano-transistor

One of the primary means for improving performance and increasing the scale of integration on a chip is the miniaturization of the electronic devices that comprise it. The SIA roadmap projects that future gains in performance will continue to accrue from this approach. One of the guiding principles for miniaturization has been the scaling of successful existing device designs to smaller dimensions. While there may be no compelling reason why the SIA targets cannot be achieved by continued scaling, an accurate assessment of the limiting performance that can be derived from conventional CMOS is crucial for identifying the principal impediments and for developing alternatives. Here, we identify five impediments that we have encountered as we attempt to scale CMOS technology toward 10 nm gate lengths: optical lithography, gate oxide tunneling, enhanced boron diffusion in the ultra-shallow junction, drive current saturation with decreasing oxide thickness, and the subthreshold current.

Progress toward 10 nm CMOS devices

https://www3.nd.edu/~gtimp/images/Relentless_sdarticle(5).pdf

K.K. Bourdelle

Papers

The ballistic nano-transistor

Progress toward 10 nm CMOS devices

The relentless march of the MOSFET gate oxide thickness to zero