The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors. When two-dimensional (2-D) electrostatic effects are small (and when the insulator capacitance is much less than the semiconductor (quantum) capacitance), the model reduces to Natori's theory of the ballistic MOSFET. The model also treats 2-D electrostatics and the quantum capacitance limit where the semiconductor quantum capacitance is much less than the insulator capacitance. This new model provides insights into the performance of MOSFETs near the scaling limit and a unified framework for assessing and comparing a variety of novel transistors.

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Theory of ballistic nanotransistors

The field of plasma etching is reviewed. Plasma etching, a revolutionary extension of the technique of physical sputtering, was introduced to integrated circuit manufacturing as early as the mid 1960s and more widely in the early 1970s, in an effort to reduce liquid waste disposal in manufacturing and achieve selectivities that were difficult to obtain with wet chemistry. Quickly, the ability to anisotropically etch silicon, aluminum, and silicon dioxide in plasmas became the breakthrough that allowed the features in integrated circuits to continue to shrink over the next 40 years. Some of this early history is reviewed, and a discussion of the evolution in plasma reactor design is included. Some basic principles related to plasma etching such as evaporation rates and Langmuir–Hinshelwood adsorption are introduced. Etching mechanisms of selected materials, silicon, silicon dioxide, and low dielectric-constant materials are discussed in detail. A detailed treatment is presented of applications in current silicon integrated circuit fabrication. Finally, some predictions are offered for future needs and advances in plasma etching for silicon and nonsilicon-based devices.

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Plasma etching: Yesterday, today, and tomorrow

The device physics of nanoscale MOSFETs is explored by numerical simulations of a model transistor. The physics of charge control, source velocity saturation due to thermal injection, and scattering in ultrasmall devices are examined. The results show that the essential physics of nanoscale MOSFETs can be understood in terms of a conceptually simple scattering model.

Essential physics of carrier transport in nanoscale MOSFETs

Quantization in the inversion layer and phase coherent transport are anticipated to have significant impact on device performance in “ballistic” nanoscale transistors. While the role of some quantum effects have been analyzed qualitatively using simple one-dimensional ballistic models, two-dimensional (2D) quantum mechanical simulation is important for quantitative results. In this paper, we present a framework for 2D quantum mechanical simulation of a nanotransistor/metal oxide field effect transistor. This framework consists of the nonequilibrium Green’s function equations solved self-consistently with Poisson’s equation. Solution of this set of equations is computationally intensive. An efficient algorithm to calculate the quantum mechanical 2D electron density has been developed. The method presented is comprehensive in that treatment includes the three open boundary conditions, where the narrow channel region opens into physically broad source, drain and gate regions. Results are presented for (i) dr...

Two-dimensional quantum mechanical modeling of nanotransistors

The percent dissociation of Cl2 was determined for two configurations of a commercial transformer-coupled plasma (TCP) reactor (LAM Research Alliance metal etcher), using Cl2 and BCl3/Cl2 feed gases, during slow etching of SiO2 covered Si wafers. Emission from Cl2 at 305 nm was recorded as a function of TCP source power, along with emission from 1% Ar and Xe, added as part of an equal mixture of the five rare gases. Absolute Cl2 number densities were determined from the Cl2-to-rare gas emission intensity ratios. The Cl2 percent dissociation increases with power, reaching 70% between 1 and 2 mTorr at the highest power (900 W, 0.080 W/cm3). The percent dissociation decreases with increasing pressure between 1 and 10 mTorr. Decreasing the gap between the TCP window and the wafer chuck from 11 to 6.5 cm decreases dissociation at pressures between 0.5 and 2 mTorr, and increases dissociation slightly at 10 mTorr. The percent dissociation as a function of power, and for the most part as a function of pressure and gap, is reproduced by a zero-dimensional model that includes electron-impact dissociation and dissociative attachment of Cl2, and diffusion-controlled recombination of Cl at the walls. Addition of BCl3 to Cl2 increases the percent dissociation of Cl2, most likely due to a passivation of the chamber walls by adsorbed BClx, lowering the Cl-atom recombination coefficient.

Percent dissociation of Cl2 in inductively coupled, chlorine-containing plasmas

We have achieved extremely high drive current performance and ballistic (T>0.8) transport using ultra-thin (<2 nm) gate oxides in sub-30 nm effective channel length nMOSFETs. The peak drive performance in an nMOSFET was observed at t/sub ox//spl ap/1.3 nm for a 1.5 V power supply voltage with T/sub n//spl ap/0.7, while the peak performance in a pMOSFET was observed at t/sub ox//spl ap/1.5 nm for a -1.5 V supply with T/sub p//spl ap/0.5. Since the carrier scattering in the channel is due predominately to interface roughness, reducing the transverse surface field, either by reducing the gate voltage or by increasing the oxide thickness, can be used to improve the transmittance T/sub n//spl rarr/0.85, T/sub p//spl rarr/0.6, while diminishing the drive current.

The ballistic nano-transistor

Diffraction from a periodic structure is sensitive to small changes in the shape of that structure. It is possible to exploit this behavior of the scatter data for accurate, precise, rapid, nondestructive, and in situ measurements of grating structures. We present the use of rigorous coupled-wave theory to generate diffraction profiles to train a partial least-squares (PLS) multivariate calibration routine. The resulting PLS calibration model was applied to experimental diffraction data from gratings in etched bulk silicon to predict etch depths. A single-detector scanning scatterometer was used to measure the scatter from 32-μm-pitch structures illuminated with a He–Ne laser beam. The scatterometer measured the diffraction patterns from grating structures at 14 die locations on each of a set of five wafers. The theoretically based PLS estimator was then used to predict etch depths from scatterometry data obtained from the 70 different grating structures. The etch depth predictions were in excellent agreement with those obtained with a scanning force microscope (i.e., 0.9-μm-deep structures were predicted with an average error of 0.007 μm). This is a significant step toward the solution of the parametric inverse grating diffraction problem: that of quantitative prediction of structure dimensions from the measurement of scatter data.

Etch depth estimation of large-period silicon gratings with multivariate calibration of rigorously simulated diffraction profiles

We have investigated a new class of high K gate dielectric materials, Si-doped aluminates These dielectrics, with TiN gates, can withstand high temperature CMOS processing and therefore do not require replacement gate technology In this paper we focus on Si-doped zirconium aluminate (Zr-Al-Si-O), with K/spl sim/20 With the TiN gate stack subjected to the standard CMOS thermal budget, we have scaled this dielectric to t/sub eq//spl sim/12 nm with leakage current 15) may be viable alternate gate dielectrics

Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applications

As device design rules continue to shrink for the manufacturing of integrated circuits, unprecedented challenges for process inspection appear. No longer is optical microscopy adequate for determining if process results meet specifications. On the other hand, the alternative—scanning electron microscopy—is time consuming, destructive, and costly. Another approach is to measure scattered light intensity as a function of scattering angle, as opposed to imaging, to obtain distinct signatures for submicron structures. In this work, a set of Si wafers with photolithographically defined lines and spaces are reactively ion etched. By varying process conditions, a range of depths and sidewall profiles is generated and then inspected by detecting visible scattered laser light over 180°. The resultant scattergrams are then analyzed both by using discriminant analysis and by training a neural network to catalog the microstructures according to depth and profile. We find that this approach is a viable alternative to ...

A. Kornblit

Papers

Percent dissociation of Cl2 in inductively coupled, chlorine-containing plasmas

The ballistic nano-transistor

Etch depth estimation of large-period silicon gratings with multivariate calibration of rigorously simulated diffraction profiles

Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applications

Reactive ion etching profile and depth characterization using statistical and neural network analysis of light scattering data