We report a new NBTI phenomenon for p-MOSFETs with ultra thin gate oxides. We demonstrate that in a CMOS inverter circuit, the interface traps generated under NBTI stressing in a p-MOSFET (corresponding to the "high" output state of the inverter) are subsequently passivated when the gate to drain voltage switches to positive (corresponding to the "low" output state of the inverter). As a result, it was found that this "Dynamic" NBTI (DNBTI) operating in a CMOS inverter circuit prolongs significantly the device lifetime while the conventional "static" NBTI (SNBTI) underestimates the device lifetime. Furthermore, the DNBTI effect is dependent on temperature and gate oxide thickness, but independent of operation frequency. A physical model is proposed for DNBTI that involves the interaction between hydrogen and silicon dangling bonds. This finding has significant impact on the determination of maximum operation voltage as well as lifetime projection for future scaling of CMOS devices.

Dynamic NBTI of PMOS transistors and its impact on device lifetime

For the first time, a dynamic negative bias temperature instability (DNBTI) effect in p-MOSFETs with ultrathin gate oxide (1.3 nm) has been studied. The interface traps generated under NBTI stressing corresponding to p-MOSFET operating condition of the "high" output state in a CMOS inverter, are subsequently passivated when the gate to drain voltage switches to positive corresponding to the p-MOSFET operating condition of the "low" output state in the CMOS inverter. Consequently, this DNBTI effect significantly prolongs the lifetime of p-MOSFETs operating in a digital circuit, and the conventional static NBTI (SNBTI) measurement underestimates the p-MOSFET lifetime. A physical model is presented to explain the DNBTI. This finding has significant impact on future scaling of CMOS devices.

Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling

The influence of Hf-based dielectrics on the underlying SiO2 interfacial layer (IL) in high-k gate stacks is investigated. An increase in the IL dielectric constant, which correlates to an increase of the positive fixed charge density in the IL, is found to depend on the starting, pre-high-k deposition thickness of the IL. Electron energy-loss spectroscopy and electron spin resonance spectra exhibit signatures of the high-k-induced oxygen deficiency in the IL consistent with the electrical data. It is concluded that high temperature processing generates oxygen vacancies in the IL responsible for the observed trend in transistor performance.

The effect of interfacial layer properties on the performance of Hf-based gate stack devices

Reaction-Diffusion (R-D) framework for interface trap generation along with hole trapping in pre-existing and generated bulk oxide traps are used to model Negative Bias Temperature Instability (NBTI) in differently processed SiON p-MOSFETs. Time, temperature and bias dependent degradation and recovery transients are predicted. Long-time power law exponent of DC degradation and uniquely renormalized duty cycle and frequency dependent AC degradation data from a wide range of sources are shown to have universal features and a broad consensus across industry/academia. These universal features can also be predicted using the classical R-D framework.

A critical re-evaluation of the usefulness of R-D framework in predicting NBTI stress and recovery

This paper examines the atomic-scale defects involved in a metal-oxide-silicon field-effect-transistor reliability problem called the negative-bias temperature instability (NBTI). NBTI has become the most important reliability problem in modern complementary-metal-oxide-silicon technology. Despite 40 years of research, the defects involved in this instability were undetermined prior to this paper. We combine DC gate-controlled diode measurements of interface-state density with two very sensitive electrically detected magnetic-resonance measurements called spin-dependent recombination (SDR) and spin-dependent tunneling (SDT). An analysis of these measurements provides an identification of the dominating atomic-scale defects involved in NBTI in pure- and plasma-nitrided oxide (PNO)-based devices. We are also able to observe atomic-scale defects involved in HfO2-based devices (although a definitive identification of the dominating defects structure was not possible). Our results in pure- devices indicate an NBTI mechanism which is dominated by the generation of Pb0 and Pb1 interface-state defects. (Pb0 and Pb1 are both silicon dangling-bond defects, in which the central silicon is back-bonded to three other silicon atoms precisely at the interface). This observation is consistent with what most NBTI researchers have assumed. However, our observations in PNO devices contradict with what most NBTI researchers had previously assumed. We demonstrate that the dominating NBTI-induced defect in the plasma-nitrided devices is fundamentally different than those observed in pure-based devices. Our measurements indicate that the new plasma-nitrided NBTI-induced defect's physical location extends into the gate dielectric. The defect participates in both SDR and SDT. Our SDR results strongly indicate that the plasma-nitrided defect has a density of states which is more narrowly peaked than that of centers and is near the middle of the band gap. The high sensitivity of our SDT measurements allow an identification of the physical and chemical nature of this defect through observations of hyperfine interactions. The defects are silicon dangling bonds, in which the central silicon is back-bonded to nitrogen atoms. We call these NBTI-induced defects centers because of the similarities to the centers observed in silicon nitride (the silicon-nitrided center is also a silicon dangling bond in which the silicon atom is back-bonded to nitrogen atoms). The defect identification in plasma-nitrided devices helps to explain the following phenomena: (1) NBTI's enhancement in plasma-nitrided devices; (2) conflicting reports of NBTI-induced interface states and/or bulk traps; and (3) fluorine's ineffectiveness in reducing NBTI in plasma-nitrided devices. We also observe the atomic-scale defects involved in NBTI in HfO2-based devices and find that short- and long-term stressing generates different defects and that these defects are different than those observed in the SiO2 and plasma-nitrided devices. Our results also suggest that the NBTI-induced defects in these devices are physically located in the interfacial layer (not at the interface).

Atomic-Scale Defects Involved in the Negative-Bias Temperature Instability

A direct-current current-voltage (DCIV) measurement technique of interface and oxide traps on oxidized silicon is demonstrated It uses the gate-controlled parasitic bipolar junction transistor of a metal-oxide-silicon field-effect transistor in a p/n junction isolation well to monitor the change of the oxide and interface trap density The dc base and collector currents are the monitors, hence, this technique is more sensitive and reliable than the traditional ac methods for determination of fundamental kinetic rates and transistor degradation mechanisms, such as charge pumping >

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Direct-current measurements of oxide and interface traps on oxidized silicon

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 /spl mu/m n-channel Si MOS transistor with about 10/sup 11/ traps/cm/sup 2/ generated by channel hot electron stress.

Profiling interface traps in MOS transistors by the DC current-voltage method

Positive oxide charge build up (+Q/sub OT/) during channel-hot-electron (CHE) stress in silicon n-channel MOS transistors from 1.0 and 0.35-/spl mu/m technologies is monitored by the direct-current current-voltage (DCIV) method. Experiments demonstrated the following: (1) +Q/sub OT/ is located over the drain/channel junction space-charge-region, (2) threshold hole kinetic energy equals the SiO/sub 2//Si hole barrier, /spl phi//sub Xh/=4.25 eV, (3) the oxide-charging carriers near the threshold are the secondary hot holes generated by interband impact-collision and Auger-recombination of the CHEs with thermalized holes impact-generated in the n/sup +/ drain by CHEs, and (4) the smallest threshold drain acceleration voltage from interband Auger-recombination among the four intrinsic pathways is smaller than /spl phi//sub Xh/ by E/sub Gap/-Sl, 4.25 V-1.12 V=3.13 V.

Positive oxide charge from hot hole injection during channel-hot-electron stress

Reduction of the interface trap density over the p-channel of MOS transistors during channel hot hole stress is observed from DCIV measurements. A proposed model consists of hydrogenation of the residual interfacial bonds by hydrogen and the hydrogen is released from the hydrogenated boron in the p/sup +/drain region by the channel hot holes.

Reduction of interface traps in p-channel MOS transistors during channel-hot-hole stress

A channel hot carrier current and the failure rate of n- and p-channel MOS transistors are both increased by one to two orders of magnitude by forward biasing the substrate or source pin junction. Correlations with the hydrogen-bond-breaking theory give a threshold kinetic energy of 3.06/spl plusmn/0.05 eV for interface trap generation by hot carriers.

K.M. Han

Papers

Direct-current measurements of oxide and interface traps on oxidized silicon

Profiling interface traps in MOS transistors by the DC current-voltage method

Positive oxide charge from hot hole injection during channel-hot-electron stress

Reduction of interface traps in p-channel MOS transistors during channel-hot-hole stress

Current-accelerated channel hot carrier stress of mos transistors