A high-speed 16-Mb DRAM chip with on-chip error-correcting code (ECC), which supports either 11/11 or 12/0 RAS/CAS addressing and operates on a 3.3- or 5-V power supply, is described. It can be packaged as a 2-Mb*8, 4-Mb*4, 8-Mb*2, or 16-Mb*1 DRAM, And is capable of operating in fast page mode, static column mode, or toggle mode. Speed and flexibility are achieved by a pipeline layout and on-chip SRAMs that buffer entire ECC words. The use of redundant word and bit lines in conjunction with the ECC produces a synergistic fault-tolerance effect. >

A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC

A 5 V-only 64K dynamic RAM is designed and fabricated using double poly-Si technology based on the 3 /spl mu/m design rule. The design features of this dynamic RAM are described. In particular, memory cell and S/N (signal/noise) designs are focused of a dynamic RAM with an on-chip bias generator. The device fabricated provides a typical access time of 120 ns and a 170 mW operating power, with minimized sense noise of less than 50 mV.

A 5 V-only 64K dynamic RAM based on high S/N design

MOSFETs in the sub-0.1- mu m regime were investigated using a nonplanar device simulator CADDETH-NP. It was found that even in this regime, the short-channel effect can be suppressed in grooved gate MOSFETs because of the concave corner of the gate insulator. MOSFETs with a gate length of 0.05 mu m or less with no threshold voltage lowering can be made by optimizing the concave corner radius, junction depths, and channel doping. >

Simulation of sub-0.1- mu m MOSFETs with completely suppressed short-channel effect

Grooved-gate Si MOSFET's with tungsten gates are fabricated using conventional manufacturing technologies, and their short-channel-effect-free characteristics are verified down to a source and drain separation of around 0.1 /spl mu/m. Phase shift lithography followed by a side-wall oxide film formation technique achieves a spacing of less than 0.2 /spl mu/m between adjacent elevated polysilicons, subsequently resulting in a sub-0.1-/spl mu/m source and drain separation in the substrate. Short-channel effects, such as threshold voltage roll-off and punchthrough, are found to be completely suppressed. From device simulations, the potential barrier formed at each grooved-gate corner is considered to be responsible for the suppression of the short-channel effects. >

Short-channel-effect-suppressed sub-0.1-/spl mu/m grooved-gate MOSFET's with W gate

Derives a new formula for the sensitivity of a vertically matched CMOS sense amplifier, of the type used in dynamic-RAMs (DRAMs), to threshold voltage mismatch, parasitic capacitance mismatch, transconductance mismatch, and bit-line load capacitance mismatch. The formula yields insight into the DRAM sensing operation. The authors derive a sensitivity formula for this sensing scheme, using perturbation theory. The perturbation approach is rigorous: it avoids most approximations and ad-hoc assumptions, it introduces no free constants to be determined from simulations, and it yields an explicit closed-form solution. The formula agrees well with simulations. It is inherently slightly conservative and thus appropriate for use in design. >

Mismatch sensitivity of a simultaneously latched CMOS sense amplifier

The electrical characteristics of the concave MOSFET are analyzed by the two-dimensional numerical method and the theoretical result is in reasonable agreement with the experimental result. Even if the channel length of the concave MOSFET is short, the obtained current-voltage characteristics of the concave MOSFET are quite similar to those of the long-channel normal MOSFET and can be approximated by the normal MOSFET formula. In short-channel concave MOSFET's, the threshold voltage lowering due to the short-channel effect is not observed. It is observed that the threshold voltage of the concave MOSFET depends strongly on the substrate bias voltage as compared with the long-channel normal MOSFET. These observed results are followed by the two-dimensional numerical analysis. The increase of the punch-through breakdown voltage as well as that of the surface induced avalanche breakdown voltage of the concave MOSFET is predicted theoretically. The equivalent circuit model of the concave MOSFET is shown and discussed.

An analysis of the concave MOSFET

An approximate analytic expression for the sensitivity of a dynamic flip-flop sense amplifier is derived. The calculation includes the imbalance of the flip-flop, and the approximate solution is given by means of Lynch and Boll's method. The sensitivity, which is defined by the minimum difference in input voltages, consists of two terms; one is the center voltage deviation, which is characterized by the imbalance of the device parameters, and the other is the insensitivity-width term, which greatly depends on the choice of circuit parameters. In normal highly sensitive sense amplifiers used in dynamic memories, the insensitivity-width term can be sufficiently small and the sensitivity is dominated by the imbalance of device parameters such as threshold voltages, conductances, and capacitances.

Sensitivity of dynamic MOS flip-flop sense amplifiers

A 65536 word/spl times/1 bit dynamic random access memory is developed using 4 /spl mu/m design rules, a 320-/spl Aring/ thick gate oxide film, and an improved double-poly n-channel silicon gate process. The chip is successfully encapsulated in a standard 16-pin dual-in-line ceramic package, and is able to take over the place that the current 16 Kbit dynamic RAM has occupied. It realizes high speed operation with access time of less than 100 ns and low power dissipation of less than 300 mW.

A 64 Kbit MOS dynamic random access memory

A 65 536 word \times 1 bit dynamic random access memory is developed using 4 µm design rules, a 320-A thick gate oxide film, and an improved double-poly n-channel silicon gate process. The chip is successfully encapsulated in a standard 16-pin dual-in-line ceramic package, and is able to take over the place that the current 16 kbit dynamic RAM has occupied. It realizes high speed operation with access time of less than 100 ns and low power dissipation of less than 300 mW.

K. Natori

Papers

An analysis of the concave MOSFET

Sensitivity of dynamic MOS flip-flop sense amplifiers

A 64 Kbit MOS dynamic random access memory

A 64 kbit MOS dynamic random access memory