Recent changes in how people consume multimedia services are causing an explosive increase in mobile traffic. With more and more people using wireless networks, the demand for the ultra-fast wireless communications systems is increasing. To date, this demand has been accommodated with advanced modulation schemes and signal-processing technologies at microwave frequencies. However, without increasing the carrier frequencies for more spectral resources, it may be quite difficult to keep up with the needs of users. Although there are several alternative bands, recent advances in terahertz-wave (THz-wave) technologies have attracted attention due to the huge bandwidth of THz waves and its potential for use in wireless communications. The frequency band of 275 ~ 3000 GHz , which has not been allocated for specific uses yet, is especially of interest for future wireless systems with data rates of 10 Gb/s or higher. Although THz communications is still in a very early stage of development, there have been lots of reports that show its potential. In this review, we will examine the current progress of THz-wave technologies related to communications applications and discuss some issues that need to be considered for the future of THz communications.

Present and Future of Terahertz Communications

This tutorial presents an overview of the technological advances in millimeter-wave (mm-wave) circuit components, antennas, and propagation that will soon allow 60-GHz transceivers to provide multigigabit per second (multi-Gb/s) wireless communication data transfers in the consumer marketplace. Our goal is to help engineers understand the convergence of communications, circuits, and antennas, as the emerging world of subterahertz and terahertz wireless communications will require understanding at the intersections of these areas. This paper covers trends and recent accomplishments in a wide range of circuits and systems topics that must be understood to create massively broadband wireless communication systems of the future. In this paper, we present some evolving applications of massively broadband wireless communications, and use tables and graphs to show research progress from the literature on various radio system components, including on-chip and in-package antennas, radio-frequency (RF) power amplifiers (PAs), low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers, and analog-to-digital converters (ADCs). We focus primarily on silicon-based technologies, as these provide the best means of implementing very low-cost, highly integrated 60-GHz mm-wave circuits. In addition, the paper illuminates characterization techniques that are required to competently design and fabricate mm-wave devices in silicon, and illustrates effects of the 60-GHz RF propagation channel for both in-building and outdoor use. The paper concludes with an overview of the standardization and commercialization efforts for 60-GHz multi-Gb/s devices, and presents a novel way to compare the data rate versus power efficiency for future broadband devices.

http://faculty.poly.edu/~tsr/wp-content/uploads/publications/abstract17.pdf

State of the Art in 60-GHz Integrated Circuits and Systems for Wireless Communications

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT/fMAX of 120 GHz/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB bandwidth >13 GHz, a P 1dB of +6.4 dBm with 7% PAE and a saturated output power of +9.3 dBm at 60 GHz. The LNA represents the first 90-nm CMOS implementation at 60 GHz and demonstrates improvements in noise, gain and power dissipation compared to earlier 60-GHz LNAs in 160-GHz SiGe HBT and 0.13-mum CMOS technologies. It features 14.6 dB gain, an IIP 3 of -6.8 dBm, and a noise figure lower than 5.5 dB, while drawing 16 mA from a 1.5-V supply. The use of spiral inductors for on-chip matching results in highly compact layouts, with the total PA and LNA die areas with pads measuring 0.35times0.43 mm2 and 0.35times0.40 mm2, respectively

Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio

A fully-integrated FMCW radar system for automotive applications operating at 77 GHz has been proposed. Utilizing a fractional- synthesizer as the FMCW generator, the transmitter linearly modulates the carrier frequency across a range of 700 MHz. The receiver together with an external baseband processor detects the distance and relative speed by conducting an FFT-based algorithm. Millimeter-wave PA and LNA are incorporated on chip, providing sufficient gain, bandwidth, and sensitivity. Fabricated in 65-nm CMOS technology, this prototype provides a maximum detectable distance of 106 meters for a mid-size car while consuming 243 mW from a 1.2-V supply.

A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology

This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1 m wireless link at 4 Gb/s QPSK with less than 10-11 BER.

A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry

A 75-to-91 GHz receiver front-end, consisting of a three-stage cascode low-noise amplifier (LNA), a double-balanced Gilbert-cell mixer and a differential DC-to-9 GHz IF buffer, is reported in 65-nm general purpose (GP) CMOS technology. The noise and input-impedance matched LNA employs a cascode input stage with shunt-series, transformer feedback. A theoretical and experimental comparison with a conventional inductor-feedback LNA indicates 0.5-1 dB higher gain, 0.3-0.6 dB lower noise figure and better input return loss for the transformer feedback LNA. The receiver has a differential down-conversion gain of 13 dB, an input P1dB of -16.2 dBm, and a double-sideband noise figure of 8.5 to 10 dB at an IF of 1 GHz. Because of the transformer feedback, the input return loss is better than -20 dB from 80 to 92 GHz and remains below -10 dB from 70 GHz beyond 95 GHz. The circuit occupies an area of 460 mum times 500 mum and consumes 89 mW (47 mW in the LNA and mixer) from a 1.5 V supply. An LO-to-RF isolation of 60 dB was measured for LO signals in the 80-to-85 GHz range. Measurements of the mixer breakout, which includes transformers at the RF and LO ports, show a record NFDSB of 8 to 10 dB over the 74-to-91 GHz band. The 50-Omega noise figure of the LNA is 6.4 to 8.4 dB in the 75-to-88.5 GHz range. The LNA can also be employed as a transmitter output stage with a saturated output power of +4 dBm.

/pdf/a-wideband-w-band-receiver-front-end-in-65-nm-cmos-3dk49rykm8.pdf

A Wideband W-Band Receiver Front-End in 65-nm CMOS

This paper presents a 1.2 V, 100 mW, 140 GHz receiver with on-die antenna in a 65 nm General Purpose (GP) CMOS process with digital back-end. The receiver has a conversion loss of 15-19 dB in the 100-140 GHz range with 102 GHz LO, and occupies a die area of only 580 mum times 700 mum including pads. The LNA achieves 8 dB gain at 140 GHz, 10 GHz bandwidth, at least -1.8 dBm of saturated output power, and maintains 3 dB gain at 125 degC. The on-chip antenna, which meets all density fill requirements of 65 nm CMOS, has -25 dB gain, and occupies 180 mum times 100 mum of die area. Additionally, design techniques which maximize the millimeter-wave performance of CMOS devices are discussed.

A 1.2V, 140GHz receiver with on-die antenna in 65nm CMOS

This paper presents a fully integrated receiver, with LNA, mixer, IF amplifier, fundamental-frequency quadrature VCO, and static frequency divider, operating at 95GHz in a 65nm general-purpose (GP) CMOS technology. The receiver consumes 206mW from a 1.2V/1.5V supply. With large RF and IF bandwidths of over 19GHz and 16GHz, respectively, it is suitable for passive-imaging applications, and for wireless chip-to-chip communication at data-rates exceeding 20Gb/s. Together with the recently reported 60GHz receiver in 90nm CMOS, this 95GHz receiver in 65nm CMOS demonstrates that scaling of entire mm-wave receivers is possible in both frequency coverage and across technology nodes.

/pdf/a-95ghz-receiver-with-fundamental-frequency-vco-and-static-2ze0c61p3c.pdf

A 95GHz Receiver with Fundamental-Frequency VCO and Static Frequency Divider in 65nm Digital CMOS

A single-chip transceiver with on-die transmit and receive antennas, Rx and Tx amplifiers, 165-GHz oscillator and static frequency divider is reported in a SiGe HBT process with fT/fMAX of 270 GHz/340 GHz. This marks the highest frequency transceiver in silicon and the highest level of functional integration above 100 GHz in any semiconductor technology. The downconversion gain peaks at -5 dB and the transmit power is -5 dBm when measured at the transceiver pads. Both degrade by approximately 25 dB when measured above the antennas of the transceiver with on-die antennas. The experimental performance of dipole (with and without floating metal strips) and patch antennas is also investigated. The measured 15-dB gain of a standalone amplifier is centered at 170 GHz and remains higher than 10 dB from 160 GHz to 180 GHz while the saturated output power is 0 dBm at 165 GHz.

/pdf/170-ghz-transceiver-with-on-chip-antennas-in-sige-technology-2lj1i688q2.pdf

K.W. Tang

Papers

Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio

A Wideband W-Band Receiver Front-End in 65-nm CMOS

A 1.2V, 140GHz receiver with on-die antenna in 65nm CMOS

A 95GHz Receiver with Fundamental-Frequency VCO and Static Frequency Divider in 65nm Digital CMOS

170-GHz transceiver with on-chip antennas in SiGe technology