K
Kamalika Datta
Researcher at National Institute of Technology, Meghalaya
Publications - 87
Citations - 907
Kamalika Datta is an academic researcher from National Institute of Technology, Meghalaya. The author has contributed to research in topics: Logic gate & Logic synthesis. The author has an hindex of 15, co-authored 69 publications receiving 676 citations. Previous affiliations of Kamalika Datta include Indian Institute of Technology Kharagpur & KIIT University.
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Journal ArticleDOI
A Scalable In-Memory Logic Synthesis Approach Using Memristor Crossbar
TL;DR: A scalable design flow for in-memory computing has been proposed, where a given multioutput logic function is synthesized as a netlist of NOT/NOR gates and then mapped to the crossbar using the Memristor-Aided loGIC (MAGIC) design style.
Proceedings ArticleDOI
BDD based synthesis of Boolean functions using memristors
TL;DR: This paper proposes an efficient realization of 2-to-1 multiplexer using memristors and presents a synthesis methodology that represents a given Boolean function as a Reduced Ordered Binary Decision Diagram (ROBDD) and then maps the same to memristor implementation.
Journal ArticleDOI
A Heuristic for Linear Nearest Neighbor Realization of Quantum Circuits by SWAP Gate Insertion Using $N$ -Gate Lookahead
TL;DR: This paper considers a quantum circuit based on the NCV library, and proposes a better SWAP gate insertion method based on local ordering that uses an N-gate lookahead approach to reduce cost.
Journal ArticleDOI
A New Heuristic for $N$ -Dimensional Nearest Neighbor Realization of a Quantum Circuit
TL;DR: A generalized approach for combined local and global ordering of qubits have been proposed that is based on an improved heuristic for cost estimation and is also scalable.
Journal ArticleDOI
Efficient Mapping of Boolean Functions to Memristor Crossbar Using MAGIC NOR Gates
TL;DR: A general synthesis flow has been proposed using the MAGIC logic design style to map multioutput Boolean functions to memristor crossbars, realized as a netlist of NOR and NOT gates.