We present a model for AC NBTI which is based on capture and emission of charges in and out of oxide border traps. Capture and emission time constants of these traps are widely distributed from &#60;µs to >105s and have been experimentally determined. The model gives a good quantitative understanding of experimental data from alternating stress / recovery sequences. It also provides a physical understanding of all the special features seen in AC NBTI independently of technology parameters.

Understanding and modeling AC BTI

Variations in process, supply voltage and temperature (PVT) have always been an issue in Integrated Circuit (IC) Design. In digital circuits, PVT fluctuations affect the switching speed of the transistors and thus the timing of the logic. To guarantee fault-free operation for a specified clock frequency, IC designers have to quantify these uncertainties and account for them adequately. This is typically done by guard-banding, i.e. adding sufficient voltage safety margin to ensure proper working even under worst-case condition.

Sources of Variation

In deeply scaled CMOS technology, time-dependent degradation mechanisms (TDDMs), such as Bias Temperature Instability (BTI), have threatened the transistor performance, hence the overall circuit/system reliability. Two well-known attempts to model BTI mechanism are the reaction-diffusion (R-D) model and the Atomistic trap-based model. This paper presents a thorough comparative analysis of the two models at the gate-level in order to explore when their predictions are the same and when not. The comparison is done by evaluating degradation trends in a set of CMOS logic gates (e.g., INV, NAND, NOR, etc.) while considering seven attributes: 1) gate type, 2) gate drive strength, 3) input frequency, 4) duty factor, 5) non-periodicity, 6) instant degradation versus long-term aging, and 7) simulation CPU time and memory usage. The simulation results show that two models are in consistency in terms of the gate degradation trends w.r.t. the first four attributes (gate type, input frequency, etc.). For the rest of the attributes, the workload-dependent solution of the Atomistic trap-based model is superior from the point of non-periodicity and instant degradation, while the R-D model gets advantageous in case of long-term aging, and simulation CPU time and memory usage due to its lite AC periodic and duty factor dependent solution.

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Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates

The recycling of electronic components has become a major industrial and governmental concern, as it could potentially impact the security and reliability of a wide variety of electronic systems. It is extremely challenging to detect a recycled integrated circuit (IC) that is already used for a very short period of time because the process variations outpace the degradation caused by aging, especially in lower technology nodes. In this paper, we propose a suite of solutions, based on lightweight negative bias temperature instability (NBTI)-aware ring oscillators (ROs), for combating die and IC recycling (CDIR) when ICs are used for a very short duration. The proposed solutions are implemented in the 90-nm technology node. The simulation results demonstrate that our newly proposed NBTI-aware multiple pair RO-based CDIRs can detect ICs used only for a few hours.

Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling

Constant scaling in device dimensions and increasing operating temperatures and vertical electrical fields have all contributed to faster device aging due to NBTI. The problem is further compounded in SRAM cells where the devices are among the smallest for a technology node. Since NBTI degradation is a gradual process, it is proposed that if the threshold voltage increase in PMOS devices of SRAM cells can be monitored, cache arrays with failing cells can be reliably operated after reconfiguration, given available memory redundancy. Using an experimentally verified NBTI model, we study DC noise margins in conventional 6T SRAM cells, as a function of NBTI degradation, in the presence of process variations. An on-chip NBTI monitoring scheme is presented that can be embedded within conventional cache designs without affecting normal device operation, enabling the prediction of cell failure before its occurrence.

Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST

A new methodology to assess dynamic circuit performance using basic device currents is presented. In contrast to existing effective drive current calculation considering inverters only, our approach provides precise circuit delays of product-relevant NAND and NOR logic gates over a wide range of supply voltages. The relevance of currents in the linear regime for circuit performance in sub-65 nm CMOS technologies is demonstrated also experimentally by a 65% performance boost in complex multi-gate FET circuits.

An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits

In the development of MOSFETs first ‘Hot Carrier Injection’ (HCI) played an important role for reliability aspects [1,2]. With new shrinked process generations and nitrided gate oxides additionally the ‘Bias Temperature Instability’ (BTI) raised and became the most critical mechanism. Some publications even claim that HCI is negligible in main-stream applications [3–6]. But is this statement generally true or is it the result of a partial view? This paper will discuss the area of conflict regarding the importance of N/PBTI and HCI. Some typical examples will illuminate different fields of applications with one dominating damage mechanism. Specific characteristics of these circuits and operation conditions leading to an outbalance of HCI or Negative-/Positive-BTI will be carved out. Finally it will be evaluated if a general trend is observable.

HCI vs. BTI? - Neither one's out

We present the results of a test structure that allows to measure the variation of SRAM p-MOS and n-MOS transistors in a dense environment and to apply Negative Bias Temperature Instability (NBTI) stress on the p-MOS transistors. The threshold voltage (Vth) and drain current (Id) distributions of p-MOS SRAM transistors pre and post NBTI Stress are measured and analyzed. The probability density functions (PDF) of both transistor parameters Vth and Id follow a Gaussian distribution pre and post NBTI stress, but the difference in the transistor parameters of an individual device is not Gaussian distributed. The standard deviation in the difference of Vth is about 50% of the mean for the small SRAM p-MOS transistor. The impact of the additional variation induced by NBTI stress is shown for the Static Noise Margin of a 6-T SRAM cell.

A 65nm test structure for the analysis of NBTI induced statistical variation in SRAM transistors

A product-level aging monitor replicating a 40nm CMOS ARM1176 critical path is presented. The monitor enables a separation of the dominating negative bias instability (NBTI) stress, including speed recovery, and the switching-activity dependent hot carrier stress (HCS). The comprehensive analysis comprises transistor and circuit level measurements as well as simulations. The monitor results demonstrate that the overall circuit performance degradation, even at high frequencies and large switching activities, is 2% for wireless-typical operating conditions.

Highly accurate product-level aging monitoring in 40nm CMOS

BTI is shown to be the most important device degradation mechanism for combinational logic Significant benefits regarding lifetime predictions and the total effort in measurement time can be expected from measurements minimizing recovery by a short measuring delay or/and assessments being done with AC stress for applications ensuring AC operation only

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Karl Hofmann

Papers

An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits

HCI vs. BTI? - Neither one's out

A 65nm test structure for the analysis of NBTI induced statistical variation in SRAM transistors

Highly accurate product-level aging monitoring in 40nm CMOS

The impact of recovery on BTI reliability assessments