K
K. von Arnim
Researcher at Infineon Technologies
Publications - 17
Citations - 431
K. von Arnim is an academic researcher from Infineon Technologies. The author has contributed to research in topics: CMOS & Low-power electronics. The author has an hindex of 10, co-authored 17 publications receiving 421 citations. Previous affiliations of K. von Arnim include NXP Semiconductors.
Papers
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Journal ArticleDOI
Multi-gate devices for the 32 nm technology node and beyond
Nadine Collaert,A. De Keersgieter,Abhisek Dixit,Isabelle Ferain,Li-Shyue Lai,Damien Lenoble,Abdelkarim Mercha,Axel Nackaerts,Bartek Pawlak,R. Rooyackers,T. Schulz,K.T. San,N.J. Son,M.J.H. van Dal,Peter Verheyen,K. von Arnim,Liesbeth Witters,K. De Meyer,Serge Biesemans,Malgorzata Jurczak +19 more
TL;DR: The suitability of FinFET-based multi-gate devices for the 32 nm technology and beyond will be discussed and some technological challenges will be addressed.
Journal ArticleDOI
Efficiency of body biasing in 90-nm CMOS for low-power digital circuits
K. von Arnim,E. Borinski,P. Seegebrecht,H.L. Fiedler,Ralf Brederlow,Roland Thewes,Joerg Berthold,Christian Pacha +7 more
TL;DR: In this article, the efficiency of body biasing for leakage reduction and performance improvement in a 90-nm CMOS low-power technology with triple-well option is evaluated, and the impact of the zero-temperature coefficient point on static device and dynamic circuit performance is investigated.
Proceedings ArticleDOI
Multi-gate devices for the 32nm technology node and beyond
Nadine Collaert,A. De Keersgieter,Abhisek Dixit,Isabelle Ferain,L.-S. Lai,Damien Lenoble,Abdelkarim Mercha,Axel Nackaerts,Bartek Pawlak,R. Rooyackers,T. Schulz,K.T. Sar,N.J. Son,M.J.H. van Dal,Peter Verheyen,K. von Arnim,Liesbeth Witters,De Meyer,Serge Biesemans,Malgorzata Jurczak +19 more
TL;DR: The suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed and some technological challenges will be addressed.
Proceedings ArticleDOI
Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS
Christian Pacha,B. Martin,K. von Arnim,Ralf Brederlow,Doris Schmitt-Landsiedel,P. Seegebrecht,Jörg Berthold,Roland Thewes +7 more
TL;DR: A threshold voltage model is proposed to describe the observed off-current minimum in 120 nm CMOS technology, and it is shown that statistical threshold voltage variations are relevant for minimum-sized devices.
Proceedings ArticleDOI
An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits
TL;DR: In this paper, a new methodology to assess dynamic circuit performance using basic device currents is presented, in contrast to existing effective drive current calculation considering inverters only, which provides precise circuit delays of product-relevant NAND and NOR logic gates over a wide range of supply voltages.