K
Kazuyoshi Torii
Researcher at Hitachi
Publications - 97
Citations - 1797
Kazuyoshi Torii is an academic researcher from Hitachi. The author has contributed to research in topics: Dielectric & High-κ dielectric. The author has an hindex of 24, co-authored 97 publications receiving 1770 citations.
Papers
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Patent
Film forming apparatus and method
Kawahara Takaaki,Kazuyoshi Torii +1 more
TL;DR: An atomic layer deposition (ALD) apparatus capable of forming a conformal ultrathin-film layer with enhanced step coverage is described in this article, which includes an ALD reactor supporting a wafer, and a main pipe coupled with a carrier gas.
Journal ArticleDOI
Oxygen Vacancy Induced Substantial Threshold Voltage Shifts in the Hf-based High-$K$ MISFET with p+poly-Si Gates -A Theoretical Approach
Kenji Shiraishi,Keisaku Yamada,Kazuyoshi Torii,Yasushi Akasaka,Kiyomi Nakajima,Mitsuru Konno,Toyohiro Chikyow,Hiroshi Kitajima,Tsunetoshi Arikado +8 more
TL;DR: In this paper, a theoretical investigation of the origin of substantial threshold voltage (Vth) shifts observed in p+poly-Si gate Hf-based metal insulator semiconductor field effect transistors (MISFETs), by focusing on the effect of oxygen vacancy (VO) formation in HfO2, was made.
Journal ArticleDOI
Electrode‐induced degradation of Pb(ZrxTi1−x)O3 (PZT) polarization hysteresis characteristics in Pt/PZT/Pt ferroelectric thin‐film capacitors
TL;DR: In this article, the authors investigated the most serious form of damage that occurs during the integration of Pt/PZT/Pt ferroelectric capacitors, where PZT is Pb(ZrxTi1−x)O3] is the disappearance of polarization hysteresis characteristics during the passivation process.
Proceedings ArticleDOI
Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM
Naoki Tega,Hiroshi Miki,Masanao Yamaoka,Hitoshi Kume,Toshiyuki Mine,Takeshi Ishida,Yuki Mori,Renichi Yamada,Kazuyoshi Torii +8 more
TL;DR: In this paper, the impact of a random telegraph noise (RTN) on a scaled-down SRAM is shown for the first time, and the impact on SRAM margin enclosed by read/write Vth curves with or without RTN is simulated.
Patent
Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same
Jun Sugiura,Osamu Tsuchiya,Makoto Ogasawara,Fumio Ootsuka,Kazuyoshi Torii,Isamu Asano,Nobuo Owada,Mitsuaki Horiuchi,Tsuyoshi Tamaru,Hideo Aoki,Nobuhiro Otsuka,Seiichirou Shirai,Masakazu Sagawa,Yoshihiro Ikeda,Masatoshi Tsuneoka,Toru Kaga,Tomotsugu Shimmyo,Hidetsugu Ogishi,Osamu Kasahara,Hiromichi Enami,Atsushi Wakahara,Hiroyuki Akimori,Sinichi Suzuki,Keisuke Funatsu,Yoshinao Kawasaki,Tunehiko Tubone,Takayoshi Kogano,Ken Tsugane +27 more
TL;DR: In this paper, a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, is described.