A transformer-based high-order resonator is proposed to improve the locking range (LR) of the millimeter-wave injection-locked frequency dividers (ILFDs). The LR limitations on ILFDs are discussed, and the operating principles of the proposed high-order resonator are analyzed based on their flattened phase response. The inductive gain peaking technique and the tail current source requirement are further analyzed for low power considerations. Two chips are fabricated in a 65-nm CMOS process to implement the proposed techniques: the first one measures an LR of 62.9% from 27.9 to 53.5 GHz while consuming 5.8 mW from a 1-V power supply and the second chip achieves an LR of 62.7% from 32.4 to 61.9 GHz while consuming only 1.2 mW from a 0.42-V power supply. The best figure of merit can achieve up to 24.7 GHz/mW.

Analysis and Design of Ultra-Wideband mm-Wave Injection-Locked Frequency Dividers Using Transformer-Based High-Order Resonators

A frequency-tracking technique is proposed to enhance the locking range of millimeter-wave (mmW) injection-locked frequency dividers (ILFDs). An improved model is introduced for direct-injection ILFDs, based on which both the phase and gain conditions are analyzed and discussed. Moreover, a method of admittance locus is applied to obtain the design intuition for optimization and to predict the locking range accurately. Finally, with the proposed model and design methodology, a frequency-tracking ILFD is designed and fabricated in a 65-nm CMOS process, which measures a locking range of 39.2% from 53.4 to 79.4 GHz while consuming 2.9 mW from an 0.8-V power supply, which corresponds to an FoM of 8.97 GHz/mW.

Analysis and Design of a 2.9-mW 53.4–79.4-GHz Frequency-Tracking Injection-Locked Frequency Divider in 65-nm CMOS

In the preceding chapters, an attempt has been made to give a picture of the Balochi language as the product of its specific history, reflecting a variety of factors and influences: first, the North Western Iranian heritage; second, the intense contact with neighbouring languages, among which Persian has occupied a place of pre-eminent importance; and third, the dialectal diversity, echoing, among other things, the precarious ecological environment and the differing occupation of the speakers as shepherding nomads or settled farmers. The preceding pages attempt to show how these factors interact and are mirrored in the Balochi lexicon. In conclusion, the question arises of how the position of Balochi among North Western Iranian languages of past and present times may be described in the light of the issues raised. At first sight, it seems that Balochi occupies a position apart from all other Western Iranian languages since the Old Iranian stops and affricates appear as such in the Southern and Western dialects and presumably in Common Balochi, while they undergo modifications in the closely related languages Parthian and Persian.

IV. In Conclusion

Several transformer-based techniques are proposed to enhance the frequency tuning range of mm-wave voltage-controlled oscillators (VCOs) and the frequency locking range of injection-locked frequency dividers (ILFDs). Firstly, a switched-transformer VCO (ST-VCO) based on dual-band topology is proposed to increase the frequency tuning range. Secondly, transformer-distribution ILFDs (TD-ILFDs) are demonstrated to achieve much improved frequency locking range with compact chip area and low power consumption. Thirdly, the injection-saturation problem of ILFDs is identified, analyzed, and solved in this work. A VCO and three different TD-ILFDs are designed and fabricated in a 65 nm CMOS process. The proposed ST-VCO measures wide tuning range of 22.3% from 62.1 GHz to 78.3 GHz with phase noise of −112 dBc/Hz at 10 MHz offset while consuming 7.7 mW, corresponding to FoM and FoMT of −180.4 dBc/Hz and −187.4 dBc/Hz, respectively. The proposed 60-GHz TD-ILFDs measure locking range of 19.6 GHz (29.6%), 19.8 GHz (29.2%), and 3.8 GHz (6.1%) while consuming 1.44 mW, 1.44 mW, and 0.44 mW.

Analysis and Design of Wide-Band Millimeter-Wave Transformer-Based VCO and ILFDs

A 1Tb/s 3W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link

A 60-GHz injection-locked frequency divider (ILFD) fabricated in 65nm CMOS and operating at 1.2V consumes 1.65mW excluding buffers and biasing circuits, and has a measured locking range of 48.5–62.9GHz (25.9%) with 0dBm input power. The core ILFD area is 0.0157mm2. The large locking range is attributed to the use of the multi-order LC oscillator topology.

A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS

This paper presents a 10 fJ/bit inductive-coupling data link operating at 0.55 V supply voltage and a 135 fJ/cycle clock link at 0.7 V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65 nm CMOS whose nominal supply voltage is 1.2 V. A data rate of 1.1 Gb/s and a clock rate of 3.3 GHz, both with an error rate <; 10-12, are achieved at 0.55 V and 0.7 V supply voltage, respectively.

A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme

This paper presents a 20fJ/bit inductive-coupling data link and a 135fJ/cycle clock link operating at a 0.7V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65nm CMOS whose nominal supply voltage is 1.2V. A data rate of 1.1Gb/s and a clock rate of 3.3GHz, both with an error rate <10−12, are achieved at the 0.7V supply voltage.

A 0.7V 20fJ/bit inductive-coupling data link with dual-coil transmission scheme

This paper presents a 10 fJ/bit inductive-coupling data link operating at 0.55 V supply voltage and a 135 fJ/cycle clock link at 0.7 V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65 nm CMOS whose nominal supply voltage is 1.2 V. A data rate of 1.1 Gb/s and a clock rate of 3.3 GHz, both with an error rate <10 ―12 , are achieved at 0.55 V and 0.7 V supply voltage, respectively.

A 60-GHz injection-locked frequency divider (ILFD) is presented. A multi-order LC oscillator topology is proposed to enhance the locking range of the divider. A design guideline is described based on a theoretical analysis of the locking range enhancement. A test chip is fabricated in 65nm CMOS. Measured locking range with 0dBm input power is 48.5-62.9GHz (25.9%), which is 63.6% wider compared to the previously reported ILFD. Power consumption excluding buffers and biasing circuits is 1.65mW from 1.2V supply. The core ILFD area is 0.0157mm2 even with an extra pair of inductors.

Keita Takatsu

Papers

A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS

A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme

A 0.7V 20fJ/bit inductive-coupling data link with dual-coil transmission scheme

A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme

A 60-GHz injection-locked frequency divider using multi-order LC oscillator topology for wide locking range