Khalid Al-Hawaj

TL;DR: This paper proposes TraceBanking, a novel and flexible trace-driven address mining algorithm that can automatically generate efficient memory banking schemes by analyzing a stream of memory address bits and achieves competitive performance and resource usage compared to the state-of-the-art across a set of real-life benchmarks with affine memory accesses.

TL;DR: The main feature is the NoC architecture, which uses only 1881μm2 per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.

TL;DR: This paper is the first work to perform a rigorous evaluation of bit-serial vs. bit-parallel in-situ processing-in-SRAM, and shows that both approaches have similar area overheads.

TL;DR: This letter presents a 16-nm 496-core RISC-V network-on-chip (NoC) architecture, which enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.

TL;DR: The content-addressable parallel processing paradigm (CAPP) as discussed by the authors is an in-situ PIM architecture that leverages content addressable memories to realize bit-serial arithmetic and logic operations via sequences of search and update operations over multiple memory rows in parallel.