The formation of the Schottky barrier height (SBH) is a complex problem because of the dependence of the SBH on the atomic structure of the metal-semiconductor (MS) interface. Existing models of the SBH are too simple to realistically treat the chemistry exhibited at MS interfaces. This article points out, through examination of available experimental and theoretical results, that a comprehensive, quantum-mechanics-based picture of SBH formation can already be constructed, although no simple equations can emerge, which are applicable for all MS interfaces. Important concepts and principles in physics and chemistry that govern the formation of the SBH are described in detail, from which the experimental and theoretical results for individual MS interfaces can be understood. Strategies used and results obtained from recent investigations to systematically modify the SBH are also examined from the perspective of the physical and chemical principles of the MS interface.

The physics and chemistry of the Schottky barrier height

The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Surface reactions with oxygen are a fundamental cause of the degradation of phosphorene. Using first-principles calculations, we show that for each oxygen atom adsorbed onto phosphorene there is an energy release of about 2 eV. Although the most stable oxygen adsorbed forms are electrically inactive and lead only to minor distortions of the lattice, there are low energy metastable forms which introduce deep donor and/or acceptor levels in the gap. We also propose a mechanism for phosphorene oxidation involving reactive dangling oxygen atoms and we suggest that dangling oxygen atoms increase the hydrophilicity of phosphorene.

https://link.aps.org/accepted/10.1103/PhysRevLett.114.046801

Oxygen Defects in Phosphorene

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

A novel ultrathin elevated channel thin-film transistor (UT-ECTFT) made using low-temperature poly-Si is proposed. The structure has an ultrathin channel region (300 /spl Aring/) and a thick drain/source region. The thin channel is connected to the heavily doped drain/source through a lightly doped overlapped region. The lightly doped overlapped region provides an effective way to spread out the electric field at the drain, thereby reducing significantly the lateral electric field there at high drain bias. Thus, the UT-ECTFT exhibits excellent current saturation characteristics even at high bias (V/sub ds/=30 V, V/sub gs/=20 V). Moreover, the UT-ECTFT has more than two times increase in on-state current and 3.5 times reduction in off-state current compared to conventional thick channel TFT's.

A novel ultrathin elevated channel low-temperature poly-Si TFT

Layer-by-layer oxidation of Si(001) surfaces has been studied by scanning reflection electron microscopy (SREM). The oxidation kinetics of the top and second layers were independently investigated from the change in oxygen Auger peak intensity calibrated from the SREM observation. A barrierless oxidation of the first subsurface layer, as well as oxygen chemisorption onto the top layer, occurs at room temperature. The energy barrier of the second-layer oxidation was found to be 0.3 eV. The initial oxidation kinetics are discussed based on first-principles calculations.

Kinetics of Initial Layer-by-Layer Oxidation of Si(001) Surfaces

Oxidation of the Si(001) surface was studied by the first principles calculation technique with spin-polarized gradient approximation. We have clarified the apparent barrierless reaction mechanism of the backbond oxidation of the surface Si by incoming ${\mathrm{O}}_{2}$ molecules. An ${\mathrm{O}}_{2}$ molecule does not attack directly the backbond but the oxidation occurs via metastable chemisorption states on the Si surface. We have also found that the triplet-to-singlet spin conversion is crucial in explaining the incident energy dependence of the sticking probability of ${\mathrm{O}}_{2}$ molecules.

Backbond Oxidation of the Si(001) Surface: Narrow Channel of Barrierless Oxidation

An exact SOI device simulator applicable to prediction of the transistor characteristics in high-current region is developed. In the simulator, the basic two-dimensional Poisson's and current continuity equations are numerically solved under steady-state condition. To obtain a stable and rapid convergence in the numerical scheme, a newly developed alternative step solving method is implemented. Using this simulator, the drain current kink effect, a typical phenomenon for substrate-floating devices, is exactly simulated for the first time. The physical mechanism of this phenomenon is also clarified. The simulated results indicate that kink effects are suppressed by using low-lifetime SOI substrates.

Analysis of kink characteristics in Silicon-on-insulator MOSFET's using two-carrier modeling

Chemisorption of a single oxygen molecule on the Si(100) surface: Initial oxidation mechanisms

The drain breakdown phenomenon in ultra-thin-film (silicon-on-insulator) SOI MOSFETs has been studied. Two-dimensional simulation revealed that the thinning of the SOI film brings about an increase in the drain electric field due to the two-dimensional effect, causing a significant lowering in the drain breakdown voltage, as has been commonly seen in ultra-thin-film SOI MOSFETs. The simulation also showed that the lowered drain breakdown voltage recovered almost to its original value when the drain SOI thickness was restored, suggesting that the drain structure, rather than the source, plays a major role in determining the drain breakdown voltage. Experiments using an asymmetric device structure supported this hypothesis, showing that the breakdown voltage was mostly dependent on the drain structure, the initial potential barrier height at the source-SOI-body junction being only a minor factor. Transient simulation was also carried out to investigate the detailed breakdown process, showing that holes accumulate near the source-SOI-body junction at a high drain bias, eventually forward-biasing the junction. These results indicate that a careful drain design and/or proper choice of the SOI thickness as well as the supply voltage are quite important for realizing high performance of ultra-thin-film SOI MOSFETs. >

Koichi Kato

Papers

Kinetics of Initial Layer-by-Layer Oxidation of Si(001) Surfaces

Backbond Oxidation of the Si(001) Surface: Narrow Channel of Barrierless Oxidation

Analysis of kink characteristics in Silicon-on-insulator MOSFET's using two-carrier modeling

Chemisorption of a single oxygen molecule on the Si(100) surface: Initial oxidation mechanisms

Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFETs