1. Introduction and overview 2. Film stress and substrate curvature 3. Stress in anisotropic and patterned films 4. Delamination and fracture 5. Film buckling, bulging and peeling 6. Dislocation formation in epitaxial systems 7. Dislocation interactions and strain relaxation 8. Equilibrium and stability of surfaces 9. The role of stress in mass transport.

Thin Film Materials: Stress, Defect Formation and Surface Evolution

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Solder is widely used to connect chips to their packaging substrates in flip chip technology as well as in surface mount technology. At present, the electronic packaging industry is actively searching for Pb-free solders due to environmental concern of Pb-based solders. Concerning the reliability of Pb-free solders, some electronic companies are reluctant to adopt them into their high-end products. Hence, a review of the reliability behavior of Pb-free solders is timely. We use the format of “case study” to review six reliability problems of Pb-free solders in electronic packaging technology. We conducted analysis of these cases on the basis of thermodynamic driving force, time-dependent kinetic processes, and morphology and microstructure changes. We made a direct comparison to the similar problem in SnPb solder whenever it is available. Specifically, we reviewed: (1) interfacial reactions between Pb-free solder and thick metalliztion of bond-pad on the substrate-side, (2) interfacial reactions between Pb-free solder and thin-film under-bump metallization on the chip-side, (3) the growth of a layered intermetallic compound (IMC) by ripening in solid state aging of solder joints, (4) a long range interaction between chip-side and substrate-side metallizations across a solder joint, (5) electromigration in flip chip solder joints, and finally (6) Sn whisker growth on Pb-free finish on Cu leadframe. Perhaps, these cases may serve as helpful references to the understanding of other reliability behaviors of Pb-free solders.

Six cases of reliability study of Pb-free solder joints in electronic packaging technology

Damascene Cu electroplating for on-chip metallization, which we conceived and developed in the early 1990s, has been central to IBM's Cu chip interconnection technology. We review here the challenges of filling trenches and vias with Cu without creating a void or seam, and the discovery that electrodeposition can be engineered to give filling performance significantly better than that achievable with conformal step coverage. This attribute of superconformal deposition, which we call superfilling, and its relation to plating additives are discussed, and we present a numerical model that represents the shape-change behavior of this system.

Damascene Copper electroplating for chip interconnections

Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

▪ Abstract The increasingly rapid transition of the electronics industry to high-density, high-performance multifunctional microprocessor Si technology has precipitated migration to new materials alternatives that can satisfy stringent requirements. One of the recent innovations has been the substitution of copper for the standard aluminum-copper metal wiring in order to decrease resistance and tailor RC delay losses in the various hierarchies of the wiring network. This has been accomplished and the product shipped only since the fall of 1998, after more than a decade of intensive development. Critical fabrication innovations include the development of an electroplating process for the copper network, dual-damascence chem-mech polishing (CMP), and effective liner material for copper diffusion barrier and adhesion promotion. The present copper technology provides improved current-carrying capability by higher resistance to electromigration, no device contamination by copper migration, and the performance ...

Copper Metallization for High Performance Silicon Technology

We present a model which accounts for the dramatic evolution in the microstructure of electroplated copper thin films near room temperature. Microstructure evolution occurs during a transient period of hours following deposition, and includes an increase in grain size, changes in preferred crystallographic texture, and decreases in resistivity, hardness, and compressive stress. The model is based on grain boundary energy in the fine-grained as-deposited films providing the underlying energy density which drives abnormal grain growth. As the grain size increases from the as-deposited value of 0.05–0.1 μm up to several microns, the model predicts a decreasing grain boundary contribution to electron scattering which allows the resistivity to decrease by tens of a percent to near-bulk values, as is observed. Concurrently, as the volume of the dilute grain boundary regions decreases, the stress is shown to change in the tensile direction by tens of a mega pascal, consistent with the measured values. The small ...

Mechanisms for microstructure evolution in electroplated copper thin films near room temperature

Electromigration in 0.15–10 μm wide and 0.3 μm thick Cu lines deposited by physical vapor deposition has been investigated using both resistance and edge displacement techniques in the sample temperature range 255–405 °C. For wide polycrystalline lines (>1 μm), the dominant diffusion mechanism is a mixture of grain boundary and surface diffusion, while in narrow lines (<1 μm) the dominant mechanism is surface transport. The activation energy for grain-boundary transport is approximately 0.2 eV higher than that of surface transport.

Electromigration path in Cu thin-film lines

The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.

Reduced electromigration and stressed induced migration of Cu wires by surface coating

Electromigration in on-chip Cu interconnections with a selective electroless metal coating, CoWP, CoSnP, or Pd, on the top surface of Cu damascene lines has been investigated. The 10–20 nm thick metal cap significantly improves electromigration lifetime by providing protection against interface diffusion of Cu which has been the leading contributor to metal line failure by electromigration.

Chao-Kun Hu

Papers

Copper Metallization for High Performance Silicon Technology

Mechanisms for microstructure evolution in electroplated copper thin films near room temperature

Electromigration path in Cu thin-film lines

Reduced electromigration and stressed induced migration of Cu wires by surface coating

Reduced electromigration of Cu wires by surface coating