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Design Of Analog Cmos Integrated Circuits

State-of-the-art, challenges, and open issues in the integration of Internet of things and cloud computing

Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

IEEE transactions on very large scale integration (VLSI) systems

Accurate performance-degradation monitoring of nanometer MOSFET digital circuits is one of the most critical issues in adaptive design techniques for overcoming the performance degradation due to aging phenomena such as negative bias temperature instability (NBTI) and hot carrier injection (HCI). Therefore, this paper proposes new on-chip aging sensor circuits which deploy a threshold voltage detector for monitoring the performance degradation of an aged MOSFET. The new aging sensor circuits measure the threshold voltage difference between a NBTI/HCI stressed MOSFET device and a NBTI/HCI unstressed MOSFET device using an inverter chain and a phase comparator and digitalize the phase difference induced by the threshold voltage difference. The proposed sensor circuits achieve a direct correlation between the threshold voltage degradation and the phase difference (a phase difference resolution of 1 ns per 0.01 V threshold voltage shift). Also, the circuits are almost independent of temperature variation due to symmetrical circuit structures. A 45 nm CMOS technology and predictive NBTI/HCI models have been used to implement and evaluate the proposed circuits. The implemented layout size is 18.58 x 7.97 μm2; the post-layout power consumption is 18.57 μW during NBTI/HCI stress mode and 30.86 μW during NBTI/HCI measurement mode on average.

On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits

A novel power gating (PG) structure using only low-threshold-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed to extend the PG to an ultralow-voltage region ( ~ 0.3 V). The proposed structure deploys series-connected low-V th footers with two virtual ground ports and selectively chooses the logic cells for connecting them to each virtual ground port according to the delay criticality. Furthermore, additional circuitry is designed to reduce not only the subthreshold leakage current but also the gate-tunneling leakage and to reduce the wake-up time and rush current compared to the conventional PG. The total PG switch size of the proposed PG structure including the additional circuits is less than the conventional one. The simulation results are compared to those of other well-known circuit schemes and show that, in the ultralow-voltage region, the other high-V th-based PG schemes cannot be used due to the impractical delay increase and long wake-up time, whereas the proposed PG structure keeps the balance among the critical PG issues. The proposed PG is evaluated using inverter chains and ISCAS85 benchmark circuits at 0.6-V supply voltage, which are designed using 45-nm complementary metal-oxide-semiconductor predictive technology model.

Ultralow-Voltage Power Gating Structure Using Low Threshold Voltage

This paper proposes a new hybrid MOSFET/carbon nanotube FET (CNFET) power-gating (PG) method using 32 nm technology in the ultralow-voltage region (~0.4 V). Traditionally, PG is one of the most effective methods to reduce the power dissipation of systems in sleep mode, but it suffers from increased propagation delay and wake-up time due to the high-threshold voltage of power switches in the low-voltage region. In this paper, to reduce the propagation delay and wake-up time of the PG structure while keeping low leakage power in the sleep mode, the CNFET power switches are combined with silicon MOSFET logic cells. The proposed hybrid structure reduces the time gap in switching over from silicon MOSFET to CNFET technology. For the tradeoff between wake-up overhead and leakage power saving, a new four-power-mode PG structure and a new two-pass PG structure using back-gate biasing of the CNFET switches are used. The simulation results of the proposed hybrid PG at 0.4 V are compared with those of the logic blocks without PG and the MOSFET PG structure using low-threshold voltage power switches. The simulation results show that the proposed hybrid structure reduces the total leakage power by 69.07%, the rush current by 5.13%, and the delay by 5.96%, on average, compared to the conventional PG structure for ISCAS85 benchmark circuits designed in 32 nm technology. More specifically, the proposed structure reduces the total leakage by 95.85% at the cost of 3% delay penalty compared to the logic blocks without PG for ISCAS85 benchmark circuits designed in 32 nm technology.

Hybrid CMOS and CNFET Power Gating in Ultralow Voltage Design

[Purpose] To investigate whether thoracic spine mobilization added to stabilization exercises increases the muscular strength and range of motion of the thoracic vertebrae of chronic low-back pain patients. [Subjects] This study enrolled 20 patients with chronic low back pain, who were divided into two groups. Ten subjects were randomly selected for the stabilization exercise group and the remaining 10 subjects received thoracic spine mobilization in addition to performing the stabilization exercises. [Methods] The patients performed stabilization exercises and received thoracic spine mobilization for 12 weeks. The range of motion and isometric muscular strength of the vertebrae of all subjects were measured before and after the intervention. [Results] In the comparison of muscular strength before and after the intervention, the change in muscular strength of the trunk flexors in the stabilization exercise group was 16.0±7.4 Nm, and that of the thoracic spine mobilization group was 34.2±7.6 Nm, a significant difference in each group. In the post-intervention intergroup comparison, the muscular strength of trunk flexors in the stabilization exercise group was 111.1±16.9 Nm, while that of the thoracic spine mobilization group was 125.9±11.3 Nm, a significant difference. Also, the muscular strength of the trunk extensors in the stabilization exercise group was 148.9±31.8 Nm, while that of the thoracic spine mobilization group was 182.9±37.2 Nm, a significant difference. The thoracic spine flexion in the stabilization exercise group was 29.8±9 degrees, while that of the thoracic spine mobilization group was 38.7±6.9 degrees, a significant difference. However, there was no significant difference in lumbar flexion values between the two groups. [Conclusion] Thoracic spine mobilization added to a stabilization exercise increased the muscular strength of patients with chronic low back pain.

https://www.jstage.jst.go.jp/article/jpts/27/12/27_jpts-2014-821/_pdf

The effect of thoracic spine mobilization and stabilization exercise on the muscular strength and flexibility of the trunk of chronic low back pain patients.

As technology scales down, it has become one of the most critical issues in aging-tolerant nanoscale MOSFET circuit design to monitor the performance degradation of the circuits under aging stress conditions such as Negative-Bias-Temperature Instability (NBTI) and Hot-Carrier-Injection (HCI). Hence, this paper proposes a novel on-chip circuit to measure the delay degradation of stressed MOSFET digital circuits and digitalize the degradation for aging compensation. A 0.11μm CMOS technology has been used to implement and evaluate the proposed circuits.

Kyung Ki Kim

Papers

On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits

Ultralow-Voltage Power Gating Structure Using Low Threshold Voltage

Hybrid CMOS and CNFET Power Gating in Ultralow Voltage Design

The effect of thoracic spine mobilization and stabilization exercise on the muscular strength and flexibility of the trunk of chronic low back pain patients.

On-Chip Delay Degradation Measurement for Aging Compensation